专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20130049179A1 LOW COST HYBRID HIGH DENSITY PACKAGE 有权
公开(公告)号：US20130049179A1
公开(公告)日：2013-02-28
申请号：US13216918
申请日：2011-08-24
申请人： Kishor Desai , Qwai H. Low , Chok J. Chia , Charles G. Woychik , Huailiang Wei
发明人： Kishor Desai , Qwai H. Low , Chok J. Chia , Charles G. Woychik , Huailiang Wei
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/49575 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/481 , H01L23/4951 , H01L23/4952 , H01L23/49531 , H01L23/49541 , H01L23/49548 , H01L23/49551 , H01L23/49811 , H01L23/49827 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48247 , H01L2224/48464 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06562 , H01L2225/06568 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

42. 发明授权

US08129759B2 Semiconductor package and method using isolated VSS plane to accommodate high speed circuitry ground isolation 有权
标题翻译：半导体封装和方法采用隔离VSS平面来适应高速电路接地隔离
公开(公告)号：US08129759B2
公开(公告)日：2012-03-06
申请号：US12625457
申请日：2009-11-24
申请人： Maurice O. Othieno , Chok J. Chia , Amar J. Amin
发明人： Maurice O. Othieno , Chok J. Chia , Amar J. Amin
IPC分类号： H01L23/52
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/48091 , H01L2224/4943 , H01L2225/06562 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
摘要翻译：本发明的实施例包括半导体集成电路封装，其包括可以具有附接到其上的集成电路管芯的衬底。该封装包括与用于接地封装的低速电路的地平面电隔离的专用高速接地层。

43. 发明授权

US06743979B1 Bonding pad isolation 有权
标题翻译：粘接垫隔离
公开(公告)号：US06743979B1
公开(公告)日：2004-06-01
申请号：US10652453
申请日：2003-08-29
申请人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
发明人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
IPC分类号： H05K506
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.
摘要翻译：一种集成电路，包括其中形成有电路的衬底，其中衬底具有外围边缘。还包括最顶层的导电层和底层导电层。外部接合焊盘设置在外圈中，并形成在最上层。内部接合焊盘设置在内圈中，并且形成在最顶层内。内部连接器将内部接合焊盘电连接到电路。内部连接器形成在下面的层中，并且具有小于内部焊盘的宽度的宽度，由此限定内部连接器之间的间隙。外部连接器将外部接合焊盘电连接到电路。外部连接器形成在下面的层中，并且具有小于内部连接器之间的间隙的宽度的宽度。

44. 发明授权

US06670214B1 Insulated bonding wire for microelectronic packaging 失效
标题翻译：用于微电子封装的绝缘接合线
公开(公告)号：US06670214B1
公开(公告)日：2003-12-30
申请号：US09687263
申请日：2000-10-12
申请人： Chok J. Chia , Owai H. Low , Ramaswamy Ranganathan
发明人： Chok J. Chia , Owai H. Low , Ramaswamy Ranganathan
IPC分类号： H01L2144
CPC分类号： H01L24/85 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/05554 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/78301 , H01L2224/8502 , H01L2224/85181 , H01L2224/8592 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01079 , H01L2924/20753 , H01L2924/06 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.
摘要翻译：一种用于绝缘接合线的方法，包括以下步骤：将接合线附接到接合焊盘，并且用绝缘液体涂覆接合线，同时将接合线通过接合工具从接合焊盘牵引到封装引线。

45. 发明授权

US5923047A Semiconductor die having sacrificial bond pads for die test 失效
标题翻译：具有用于模具测试的牺牲接合焊盘的半导体管芯
公开(公告)号：US5923047A
公开(公告)日：1999-07-13
申请号：US837618
申请日：1997-04-21
申请人： Chok J. Chia , Qwai H. Low , Maniam Alagaratnam
发明人： Chok J. Chia , Qwai H. Low , Maniam Alagaratnam
IPC分类号： G01R31/28 , H01L21/301 , H01L23/485 , H01L23/58 , H01L21/60 , H01L21/66
CPC分类号： H01L24/06 , H01L22/32 , G01R31/2884 , H01L2224/05553 , H01L2924/01013 , H01L2924/01033 , H01L2924/14
摘要： The testing of integrated circuits in a plurality of dice arranged in rows and columns in a semiconductor wafer is facilitated by effectively increasing the pitch between adjacent input/output bonding pads on each die by providing a plurality of test pads in scribing space between adjacent die. Alternate test pads are connected with alternate bonding pads on adjacent die, thereby effectively increasing the pitch of adjacent die for testing. After the integrated circuits are tested and defective circuits are marked, the wafer is scribed in the scribe space and broken to recover the individual die or integrated circuit chips.
摘要翻译：通过在相邻的管芯之间的刻划空间中提供多个测试焊盘，通过有效地增加每个管芯上相邻的输入/输出焊盘之间的间距，有助于半导体晶片中以行和列布置的多个管芯中的集成电路的测试。替代的测试焊盘与相邻裸片上的替代焊盘相连，从而有效地增加相邻裸片的间距以进行测试。在对集成电路进行测试并且标记故障电路之后，在刻划空间刻划晶片并断开晶片以恢复单独的芯片或集成电路芯片。

46. 发明授权

US4868349A Plastic molded pin-grid-array power package 失效
标题翻译：塑料成型针阵列功率封装
公开(公告)号：US4868349A
公开(公告)日：1989-09-19
申请号：US191462
申请日：1988-05-09
申请人： Chok J. Chia
发明人： Chok J. Chia
IPC分类号： H01L23/28 , H01L21/56 , H01L23/12 , H01L23/29 , H01L23/31 , H01L23/433 , H01L23/50 , H05K1/18 , H05K7/20
CPC分类号： H01L21/565 , H01L23/3121 , H01L23/4334 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01039 , H01L2924/01079 , H01L2924/15312 , H01L2924/1532 , H01L2924/181 , Y10T29/49172
摘要： A molded pin-grid-array package includes a heat sink available at the face opposite to the pins. The heat sink is secured to a printed wiring board that has plated through holes therein that form the desired pin-grip-array and wires are secured in the holes to form the package pins. The heat sink covers an aperture in the board and the semiconductor die is secured to the heat sink inside the cavity thereby formed. After the semiconductor die is attached and the bonding pads connected to the metal traces on the board, the assembly is placed in a transfer mold. Plastic encapsulant is then transfer molded to encapsulate the semiconductor die and to extend flush with the heat sink to form a skirt around the periphery of the board. This leaves the molded package with an available heat sink face for efficient cooling after the package is mounted for ultimate use.
摘要翻译：模制的针栅阵列封装包括在与引脚相对的表面处可用的散热器。散热器被固定在印刷电路板上，该印刷电路板在其中镀有通孔，形成所需的针把手阵列，电线固定在孔中以形成封装引脚。散热器覆盖板中的孔，并且半导体管芯被固定到由此形成的空腔内的散热器。在安装半导体管芯并且将焊盘连接到板上的金属迹线之后，将组件放置在转移模具中。然后将塑料密封剂转移模制以封装半导体管芯并且与散热器平齐地延伸以在板的周边形成裙部。这使得模制包装具有可用的散热器表面，用于在封装安装成最终用途之后进行有效冷却。

47. 发明授权

US06963138B2 Dielectric stack 有权
标题翻译：电介质堆
公开(公告)号：US06963138B2
公开(公告)日：2005-11-08
申请号：US10357142
申请日：2003-02-03
申请人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
发明人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
IPC分类号： H01L23/485 , H01L23/532 , H01L23/48
CPC分类号： H01L24/05 , H01L23/53295 , H01L2224/05093 , H01L2224/05556 , H01L2224/05624 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/00
摘要： An integrated circuit with a pressure resistant current carrying structure having electrically conductive layers for carrying current. A first electrically nonconductive material at least partially surrounds the electrically conductive layers, and provides electrical insulation between the electrically conductive layers. The first electrically nonconductive material has a first degree of fragility and a first dielectric constant. A second electrically nonconductive material is disposed in a pattern within the first electrically nonconductive material and between the electrically conductive layers, and provides structural support for the first electrically nonconductive material between the electrically conductive layers. The second electrically nonconductive material has a second degree of fragility that is less than the first degree of fragility and a second dielectric constant that is greater than the first dielectric constant.
摘要翻译：一种具有耐压载流结构的集成电路，其具有用于承载电流的导电层。第一非导电材料至少部分地围绕导电层，并且在导电层之间提供电绝缘。第一非导电材料具有第一程度的脆性和第一介电常数。第二非导电材料以第一非导电材料内部和导电层之间的图案设置，并为导电层之间的第一非导电材料提供结构支撑。第二非导电材料具有小于第一脆性程度的第二脆性程度和大于第一介电常数的第二介电常数。

48. 发明授权

US6114749A Integrated circuit with lead frame package having internal power and ground busses 失效
标题翻译：具有内部电源和接地总线的引线框架封装的集成电路
公开(公告)号：US6114749A
公开(公告)日：2000-09-05
申请号：US884241
申请日：1997-06-27
申请人： Chok J. Chia
发明人： Chok J. Chia
IPC分类号： H01L23/057 , H01L23/495 , H01L23/50
CPC分类号： H01L23/50 , H01L23/057 , H01L23/49531 , H01L23/49558 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/49109 , H01L2224/49171 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01057 , H01L2924/01078 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/181
摘要： An integrated circuit includes a semiconductor integrated circuit chip housed in a package providing external electrical connections for the circuit chip. The package has only a limited number of external connections available for such use. The package includes an internal buss, or plurality of busses, which are electrically connected to the circuit chip and to selected external connections of the package to improve the efficiency of utilization of external connections on the package, as well as improving operating characteristics of the integrated circuit chip by improvements to voltage and current distributions to the chip, and also eliminating in some cases the consequences of a poor quality of external electrical connection to the package itself.
摘要翻译：集成电路包括容纳在封装中的半导体集成电路芯片，为电路芯片提供外部电连接。该包装只有有限数量的外部连接可用于此类使用。该封装包括内部总线或多个母线，其电连接到电路芯片和选择的封装的外部连接，以提高封装上的外部连接的利用效率，以及改进集成的操作特性通过改善对芯片的电压和电流分布的电路芯片，并且还在某些情况下消除了与封装本身的外部电连接质量差的后果。

49. 发明授权

US5728599A Printable superconductive leadframes for semiconductor device assembly 失效
标题翻译：用于半导体器件组装的可印刷超导引线框架
公开(公告)号：US5728599A
公开(公告)日：1998-03-17
申请号：US432539
申请日：1995-08-07
申请人： Michael D. Rostoker , Mark Schneider , Chok J. Chia
发明人： Michael D. Rostoker , Mark Schneider , Chok J. Chia
IPC分类号： H01L21/48 , H01L23/495 , H01L21/283 , H01L21/58 , H01L21/60
CPC分类号： H01L24/50 , H01L21/4821 , H01L23/49579 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , Y10S505/703 , Y10S505/706 , Y10S505/741 , Y10T29/49121
摘要： Process for manufacturing a high interconnection density, fine-line, superconductive printed leadframes using thick-film screen-printing techniques, or other printing techniques. Generally, a superconductive leadframe pattern is printed on a backing substrate. Once the pattern is cured, the backing substrate, or portions thereof can be removed. The backing substrate can be a "fish paper" substrate treated with a release agent, or other substrate material which can be dissolved away, etched away, or otherwise removed. Portions of the backing substrate can be used to provide mechanical integrity for the leadframe. The leadframe fingers can be printed using a superconductive paste or a superconductive precursor paste which is subsequently treated to exhibit superconductivity.
摘要翻译：使用厚膜丝网印刷技术制造高互连密度，细线，超导印刷引线框的方法或其它印刷技术。通常，超导引线框架图案印刷在背衬基板上。一旦图案固化，背衬基底或其部分可以被去除。背衬基材可以是用脱模剂处理的“鱼纸”基材，或可以溶解掉，蚀刻掉或以其它方式除去的其它基材。背衬基板的一部分可用于为引线框架提供机械完整性。引线框指可以使用超导糊或超导前体糊进行印刷，其随后被处理以显示超导性。

50. 发明授权

US5185653A O-ring package 失效
标题翻译： O型圈包装
公开(公告)号：US5185653A
公开(公告)日：1993-02-09
申请号：US661962
申请日：1991-02-28
申请人： Andrew P. Switky , Chok J. Chia
发明人： Andrew P. Switky , Chok J. Chia
IPC分类号： H01L21/50 , H01L23/057 , H01L23/16 , H01L23/495
CPC分类号： H01L21/50 , H01L23/057 , H01L23/16 , H01L23/49558 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L24/45 , H01L24/48 , H01L2924/12042 , H01L2924/14 , H01L2924/15747
摘要： A transfer molded plastic package having a cavity for accommodating a semiconductor chip is disclosed. A leadframe assembly process is shown wherein the leadframe finger pattern is provided with a resilient or elastic O-ring bead. Top and bottom housing plates which have dimensions that are larger than the bead form the upper and lower surfaces of the package. These plates can be formed of any suitably rigid material. They may be composed of ceramic in low power devices. For high power operation at least one metal plate can be employed. The chip or chips are connected to the lead frame and, along with the top and bottom plates, is located in a transfer mold. The plates are in registy and located so that their outer edges extend beyond the O-ring bead. The mold cavities include faces which press against the plates which are held apart by the O-ring bead so that the bead is compressed by the mold closure. A plastic encapsulant is molded around the periphery of the plates so that the leadframe fingers are secured therein to become package pins.
摘要翻译：公开了一种具有用于容纳半导体芯片的空腔的转移模制塑料封装。示出了引线框架组装过程，其中引线框指状图案设置有弹性或弹性O形环珠。具有大于珠的尺寸的顶部和底部壳体板形成包装的上表面和下表面。这些板可以由任何适当刚性的材料形成。它们可以由低功率器件中的陶瓷组成。对于大功率操作，可以使用至少一个金属板。芯片或芯片连接到引线框架，并且与顶板和底板一起位于转移模具中。板被配准并且定位成使得它们的外边缘延伸超过O形圈珠。模具腔包括压靠在板上的面，这些面被O形圈珠保持分开，使得胎圈被模具盖压缩。围绕板的周边模塑塑料密封剂，使得引线框架指状物固定在其中以成为封装销。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式