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41. 发明授权

US08972769B2 Data processing apparatus and control method for controlling clock frequency based on calculated frequency-to-response-time ratios 有权
标题翻译：数据处理装置和控制方法，用于根据计算出的频率响应时间比来控制时钟频率
公开(公告)号：US08972769B2
公开(公告)日：2015-03-03
申请号：US13011712
申请日：2011-01-21
申请人： Akio Nakagawa , Hisashi Ishikawa
发明人： Akio Nakagawa , Hisashi Ishikawa
IPC分类号： G06F1/04 , G06F15/16 , G06F9/30 , G06F9/40 , G06F9/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the plurality of processing units when the operation clocks of a common frequency are supplied to the plurality of processing units, and to control a frequency of the operation clocks to be supplied to at least one of the plurality of processing units so that a plurality of measured response times become closer to each other.
摘要翻译：数据处理装置包括：多个处理单元，适于根据输入的操作时钟处理数据; 以及控制单元，其适于在向所述多个处理单元提供公共频率的操作时钟时测量所述多个处理单元的响应时间，并且控制要提供给所述多个处理单元中的至少一个的所述操作时钟的频率多个处理单元，使得多个测量的响应时间变得更接近。

42. 发明申请

US20110221409A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110221409A1
公开(公告)日：2011-09-15
申请号：US13110971
申请日：2011-05-19
申请人： Kazutoshi NAKAMURA , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi NAKAMURA , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： G05F1/00 , H03H11/26
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译：一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。

43. 发明申请

US20110197089A1 DATA PROCESSING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：数据处理装置及其控制方法
公开(公告)号：US20110197089A1
公开(公告)日：2011-08-11
申请号：US13011712
申请日：2011-01-21
申请人： Akio Nakagawa , Hisashi Ishikawa
发明人： Akio Nakagawa , Hisashi Ishikawa
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the plurality of processing units when the operation clocks of a common frequency are supplied to the plurality of processing units, and to control a frequency of the operation clocks to be supplied to at least one of the plurality of processing units so that a plurality of measured response times become closer to each other.
摘要翻译：数据处理装置包括：多个处理单元，适于根据输入的操作时钟处理数据; 以及控制单元，其适于在向所述多个处理单元提供公共频率的操作时钟时测量所述多个处理单元的响应时间，并且控制要提供给所述多个处理单元中的至少一个的所述操作时钟的频率多个处理单元，使得多个测量的响应时间变得更接近。

44. 发明授权

US07633153B2 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US07633153B2
公开(公告)日：2009-12-15
申请号：US11778516
申请日：2007-07-16
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H01L23/10
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
摘要翻译：半导体模块包括安装板。多个电源开关器件芯片通过倒装芯片接合安装在安装板上。芯片具有上表面和下表面，并且被配置为面向安装板的上表面。通过倒装芯片接合将驱动IC芯片安装在安装板上。驱动IC芯片用于驱动形成在多个功率开关器件芯片中的晶体管的栅极。多个散热构件分别位于多个功率开关器件芯片的下表面上。提供树脂构件以将单个封装中的多个功率开关器件芯片和驱动IC芯片密封。

45. 发明授权

US07503654B2 Pupil reaction ascertaining device and fatigue recovery promoting device 失效
标题翻译：瞳孔反应确定装置和疲劳恢复促进装置
公开(公告)号：US07503654B2
公开(公告)日：2009-03-17
申请号：US10593881
申请日：2005-03-16
申请人： Akio Nakagawa
发明人： Akio Nakagawa
IPC分类号： A61B3/10
CPC分类号： A61B3/032 , A61B3/0008 , A61B3/112
摘要： It is an object of the present invention to provide a pupillary reflex checking apparatus that enables a subject to check his own pupillary reflex and that keeps down cost and to provide a fatigue recovery facilitating apparatus that includes the pupillary reflex checking apparatus. The pupillary reflex apparatus of the present invention includes, as essential elements of its structure, a reflecting unit and a stimulus applying unit. Of these, the reflecting unit has a structure which includes an optical reflecting surface disposed in a plane that intersects with a visual axis of a subject such that an image of a pupil of a subject's eye is formed on the optical reflecting surface. Further, the stimulus applying unit applies a stimulus to induce the pupillary reflex in the subject. Specifically, it is possible to use a light source which gives a light stimulus to the subject's eye, such as an LED light source, an electric bulb, a strobe, or the like, as the stimulus applying unit.
摘要翻译：本发明的目的是提供一种瞳孔反射检查装置，其能够使对象检查自己的瞳孔反射并降低成本，并提供包括瞳孔反射检查装置的疲劳恢复促进装置。本发明的瞳孔反射装置包括作为其结构的基本要素的反射单元和刺激施加单元。其中，反射单元具有包括设置在与被摄体的视轴相交的平面中的光反射面的结构，使得在光反射面上形成被检眼的瞳孔图像。此外，刺激施加单元施加刺激以诱导受试者中的瞳孔反射。具体地说，作为刺激施加单元，可以使用给予对象眼睛的光刺激的光源，例如LED光源，电灯泡，闪光灯等。

46. 发明申请

US20070242223A1 Pupil Reaction Ascertaining Device and Fatigue Recovery Promoting Device 失效
标题翻译：瞳孔反应确定装置和疲劳恢复促进装置
公开(公告)号：US20070242223A1
公开(公告)日：2007-10-18
申请号：US10593881
申请日：2005-03-16
申请人： Akio Nakagawa
发明人： Akio Nakagawa
IPC分类号： A61B5/16
CPC分类号： A61B3/032 , A61B3/0008 , A61B3/112
摘要： It is an object of the present invention to provide a pupillary reflex checking apparatus that enables a subject to check his own pupillary reflex and that keeps down cost and to provide a fatigue recovery facilitating apparatus that includes the pupillary reflex checking apparatus. The pupillary reflex apparatus of the present invention includes, as essential elements of its structure, a reflecting unit and a stimulus applying unit. Of these, the reflecting unit has a structure which includes an optical reflecting surface disposed in a plane that intersects with a visual axis of a subject such that an image of a pupil of a subject's eye is formed on the optical reflecting surface. Further, the stimulus applying unit applies a stimulus to induce the pupillary reflex in the subject. Specifically, it is possible to use a light source which gives a light stimulus to the subject's eye, such as an LED light source, an electric bulb, a strobe, or the like, as the stimulus applying unit.
摘要翻译：本发明的目的是提供一种瞳孔反射检查装置，其能够使对象检查自己的瞳孔反射并降低成本，并提供包括瞳孔反射检查装置的疲劳恢复促进装置。本发明的瞳孔反射装置包括作为其结构的基本要素的反射单元和刺激施加单元。其中，反射单元具有包括设置在与被摄体的视轴相交的平面中的光反射面的结构，使得在光反射面上形成被检眼的瞳孔图像。此外，刺激施加单元施加刺激以诱导受试者中的瞳孔反射。具体地说，作为刺激施加单元，可以使用给予对象眼睛的光刺激的光源，例如LED光源，电灯泡，闪光灯等。

47. 发明授权

US07227225B2 Semiconductor device having a vertical MOS trench gate structure 失效
标题翻译：具有垂直MOS沟槽栅极结构的半导体器件
公开(公告)号：US07227225B2
公开(公告)日：2007-06-05
申请号：US10829173
申请日：2004-04-22
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933
摘要： A second semiconductor region is formed on a first semiconductor region. A third semiconductor region is formed on a part of the second semiconductor region. A trench ranges from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region. The trench penetrates the third semiconductor region, and the depth of the trench is shorter than that of a deepest bottom portion of the second semiconductor region, and the second semiconductor region does not exist under a bottom surface of the trench. A gate insulating film is formed on facing side surfaces of the trench. First and second gate electrodes are formed on the gate insulating film. The first and second gate electrodes are separated from each other. The conductive material is formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened therebetween.
摘要翻译：在第一半导体区域上形成第二半导体区域。在第二半导体区域的一部分上形成第三半导体区域。沟槽的范围从第三半导体区域的表面到第三半导体区域和第二半导体区域。沟槽穿透第三半导体区域，并且沟槽的深度比第二半导体区域的最深底部的深度短，并且第二半导体区域不存在于沟槽的底表面之下。栅极绝缘膜形成在沟槽的相对的侧表面上。在栅极绝缘膜上形成第一和第二栅电极。第一和第二栅电极彼此分离。导电材料形成在沟槽的侧表面上的第一和第二栅电极之间，绝缘膜介于其间。

48. 发明申请

US20070013351A1 Electric power unit operating in continuous and discontinuous conduction modes and control method therefor 失效
标题翻译：电力单元在连续和不连续导通模式下工作及其控制方法
公开(公告)号：US20070013351A1
公开(公告)日：2007-01-18
申请号：US11485466
申请日：2006-07-13
申请人： Toshiyuki Naka , Akio Nakagawa , Kazutoshi Nakamura
发明人： Toshiyuki Naka , Akio Nakagawa , Kazutoshi Nakamura
IPC分类号： G05F1/00
CPC分类号： H02M3/157 , H02M3/1588 , Y02B70/1466
摘要： An electronic power unit includes first and second MOS transistors and a digital control circuit. The first MOS transistor applies a voltage to the load. The second MOS transistor remains on while the first MOS transistor remains off and rectifies the current flowing in the load. The digital control circuit turns on the first transistor upon lapse of a first time interval from the time the second MOS transistor is turned off. The digital control circuit turns on the second MOS transistor upon lapse of a second time interval from the time the first MOS transistor is turned off. The digital control circuit controls the on-period of the first MOS transistor so that the voltage applied to the load is constant in a discontinuous conduction mode. The digital control circuit determines, while the voltage applied to the load is constant, an optimal value of the first time from the duty.
摘要翻译：电子功率单元包括第一和第二MOS晶体管和数字控制电路。第一个MOS晶体管向负载施加电压。第二MOS晶体管保持导通，而第一MOS晶体管保持关断并且对负载中流动的电流进行整流。数字控制电路在从第二MOS晶体管截止时起第一时间间隔开启第一晶体管。数字控制电路在从第一MOS晶体管截止时经过第二时间间隔开启第二MOS晶体管。数字控制电路控制第一MOS晶体管的导通周期，使得施加到负载的电压在不连续导通模式下是恒定的。数字控制电路在施加到负载的电压是恒定的情况下确定第一次从占空比的最佳值。

49. 发明授权

US07026214B2 Offset-gate-type semiconductor device 失效
公开(公告)号：US07026214B2
公开(公告)日：2006-04-11
申请号：US10957692
申请日：2004-10-05
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L21/00
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.

50. 再颁专利

USRE38907E1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：USRE38907E1
公开(公告)日：2005-12-06
申请号：US10452203
申请日：2003-06-02
申请人： Tomoko Matsudai , Tsutomu Kojima , Akio Nakagawa
发明人： Tomoko Matsudai , Tsutomu Kojima , Akio Nakagawa
IPC分类号： H03K5/22 , H03K5/24 , H03K17/082 , H03K17/10 , H03K17/14
CPC分类号： H03K17/102 , H03K5/2481 , H03K17/0828 , H03K17/145
摘要： The differential amplifier of a comparator circuit includes first and second n-type MOSFETs for receiving an input signal, first and second p-type MOSFETs of a current mirror circuit, and a third n-type MOSFET of a current source circuit. The output stage includes a third p-type MOSFET for transmitting a signal, and a fourth n-type MOSFET of the current source circuit. The differential amplifier further includes fifth and sixth n-type MOSFETs respectively series-connected to the first and second n-type MOSFETs. The output stage further includes a seventh n-type MOSFET series-connected to the fourth n-type MOSFET. The gates of the fifth, sixth, and seventh n-type MOSFETs are connected to voltage bias circuits. The fifth, sixth, and seventh n-type MOSFETs suppress variations in voltage at an output node caused by poor saturation characteristics of the first, second, and fourth main n-type MOSFETs.
摘要翻译：比较器电路的差分放大器包括用于接收输入信号的第一和第二n型MOSFET，电流镜电路的第一和第二p型MOSFET以及电流源电路的第三n型MOSFET。输出级包括用于传输信号的第三p型MOSFET和电流源电路的第四n型MOSFET。差分放大器还包括分别串联连接到第一和第二n型MOSFET的第五和第六n型MOSFET。输出级还包括与第四n型MOSFET串联连接的第七n型MOSFET。第五，第六和第七n型MOSFET的栅极连接到电压偏置电路。第五，第六和第七n型MOSFET抑制由于第一，第二和第四主n型MOSFET的饱和特性不良引起的输出节点的电压变化。

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