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41. 发明申请

US20060002412A1 Methods and apparatus for supporting programmable burst management schemes on pipelined buses 有权
标题翻译：在流水线总线上支持可编程突发管理方案的方法和装置
公开(公告)号：US20060002412A1
公开(公告)日：2006-01-05
申请号：US10882375
申请日：2004-06-30
申请人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark Rosenbluth
发明人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark Rosenbluth
IPC分类号： H04L12/28
CPC分类号： G06F13/36 , H04L49/101 , H04L49/102 , H04L49/15 , H04L49/45
摘要： Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes one or more shared resource targets. A scalable chassis infrastructure is used to interconnect the targets with the clusters using a crossbar interconnect configuration including pipelined command, and data buses. The interconnect includes sub-group multiplexers for each sub-group and sub-group selection multiplexers coupled to each cluster. A two-stage arbiter, operatively coupled to the targets, sub-group multiplexers, and sub-group selection multiplexers, is employed to arbitrate transaction requests issued from the masters to the targets and manage transactions. The two-stage arbiter includes a provision for supporting programmable burst management, wherein selected sub-groups can be tuned for handling short or long burst traffic.
摘要翻译：在流水线总线上支持可编程突发管理方案的方法和装置。该装置包括配置在多个群集中的多个总线主站（主站）和多个目标子组。每个目标子组包括一个或多个共享资源目标。可扩展的机箱基础架构用于使用包括流水线命令和数据总线的交叉连接配置将目标与群集互连。互连包括用于每个子组的子组多路复用器和耦合到每个集群的子组选择多路复用器。使用可操作地耦合到目标的两级仲裁器，子组多路复用器和子组选择多路复用器来仲裁从主人发送到目标的事务请求并管理事务。两级仲裁器包括用于支持可编程突发管理的规定，其中可以调整所选择的子组以处理短或长突发流量。

42. 发明申请

US20050273564A1 Memory controller 有权
标题翻译：内存控制器
公开(公告)号：US20050273564A1
公开(公告)日：2005-12-08
申请号：US10860549
申请日：2004-06-02
申请人： Sridhar Lakshmanamurthy , Alpesh Oza , Rohit Verma
发明人： Sridhar Lakshmanamurthy , Alpesh Oza , Rohit Verma
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1694
摘要： A memory controller module that includes a memory interface and at least two memory controllers, each memory controller to control a category of memory devices. A circuitry enables the at least two memory controllers to control access to memory devices based on information indicating the category or categories of the memory devices coupled to the memory interface.
摘要翻译：一种存储器控制器模块，其包括存储器接口和至少两个存储器控制器，每个存储器控制器用于控制一类存储器件。电路使得至少两个存储器控制器可以基于指示耦合到存储器接口的存储器件的类别或类别的信息来控制对存储器设备的访问。

43. 发明申请

US20140258492A1 AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE 审中-公开
标题翻译：在边界接口中聚合完成信息
公开(公告)号：US20140258492A1
公开(公告)日：2014-09-11
申请号：US14209207
申请日：2014-03-13
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
IPC分类号： H04L12/761
CPC分类号： G06F13/364 , G06F13/385 , G06F13/4265 , G06F15/7807 , G06F15/7825 , G06F2213/0038 , H04L12/28 , H04L12/54 , H04L45/00 , H04L45/16
摘要： In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从耦合到路由器的第一端点在路由器中接收请求的方法，其中该请求用于聚合完成。反过来，路由器可以将请求转发到多个目标代理，从每个目标代理接收响应，并将响应合并到聚合完成中。然后，路由器可以将聚合完成发送到第一个端点。描述和要求保护其他实施例。

44. 发明授权

US08775700B2 Issuing requests to a fabric 有权
标题翻译：向织物发出请求
公开(公告)号：US08775700B2
公开(公告)日：2014-07-08
申请号：US13248276
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4221 , G06F13/366 , G06F13/368 , G06F13/4022 , G06F15/7807 , G06F15/7864
摘要： In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括确定是否已经通过结构从源代理发送到目标代理的第一事务已经满足生产者 - 消费者排序规则，并且如果是，则从第一事务发送第一事务的第一请求源代理程序在第一个时钟周期。然后，可以以流水线的方式从源代理向结构发送第二请求用于第二事务。描述和要求保护其他实施例。

45. 发明授权

US08711875B2 Aggregating completion messages in a sideband interface 有权
标题翻译：在边带接口中聚合完成消息
公开(公告)号：US08711875B2
公开(公告)日：2014-04-29
申请号：US13248243
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
IPC分类号： H04L12/66 , H01L29/06
CPC分类号： G06F13/364 , G06F13/385 , G06F13/4265 , G06F15/7807 , G06F15/7825 , G06F2213/0038 , H04L12/28 , H04L12/54 , H04L45/00 , H04L45/16
摘要： In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从耦合到路由器的第一端点在路由器中接收请求的方法，其中该请求用于聚合完成。反过来，路由器可以将请求转发到多个目标代理，从每个目标代理接收响应，并将响应合并到聚合完成中。然后，路由器可以将聚合完成发送到第一个端点。描述和要求保护其他实施例。

46. 发明申请

US20130083794A1 Aggregating Completion Messages In A Sideband Interface 有权
标题翻译：边带接口中的聚合完成消息
公开(公告)号：US20130083794A1
公开(公告)日：2013-04-04
申请号：US13248243
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Mohan K. Nair , Joseph Murray , Rohit R. Verma , Gary J. Lavelle , Robert P. Adler
IPC分类号： H04L12/28 , H04L12/54
CPC分类号： G06F13/364 , G06F13/385 , G06F13/4265 , G06F15/7807 , G06F15/7825 , G06F2213/0038 , H04L12/28 , H04L12/54 , H04L45/00 , H04L45/16
摘要： In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从耦合到路由器的第一端点在路由器中接收请求的方法，其中该请求用于聚合完成。反过来，路由器可以将请求转发到多个目标代理，从每个目标代理接收响应，并将响应合并到聚合完成中。然后，路由器可以将聚合完成发送到第一个端点。描述和要求保护其他实施例。

47. 发明授权

US07426610B2 On-device packet descriptor cache 有权
标题翻译：设备上的数据包描述符缓存
公开(公告)号：US07426610B2
公开(公告)日：2008-09-16
申请号：US11321815
申请日：2005-12-29
申请人： Sridhar Lakshmanamurthy , Hugh Miller Wilkinson, III
发明人： Sridhar Lakshmanamurthy , Hugh Miller Wilkinson, III
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9073
摘要： In an embodiment, a method is provided. The method of this embodiment provides in response to receiving a packet at a packet processing device having a memory (“on-device memory”), storing the packet at a location in a memory not on the packet processing device (“off-device memory”); creating a packet descriptor corresponding to the packet, the packet descriptor referencing the location; storing the packet descriptor in a packet descriptor queue on the off-device memory; and storing a packet descriptor copy on the on-device memory.
摘要翻译：在一个实施例中，提供了一种方法。该实施例的方法响应于在具有存储器（“在设备存储器”）的分组处理设备处接收分组，将分组存储在不在分组处理设备上的存储器中的位置（“非设备内存” “）; 创建与分组对应的分组描述符，分组描述符引用该位置; 将所述分组描述符存储在所述非设备内存上的分组描述符队列中; 以及将包描述符副本存储在设备上的存储器上。

48. 发明申请

US20070153818A1 On-device packet descriptor cache 有权
标题翻译：设备上的数据包描述符缓存
公开(公告)号：US20070153818A1
公开(公告)日：2007-07-05
申请号：US11321815
申请日：2005-12-29
申请人： Sridhar Lakshmanamurthy , Hugh Miller Wilkinson
发明人： Sridhar Lakshmanamurthy , Hugh Miller Wilkinson
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9073
摘要： In an embodiment, a method is provided. The method of this embodiment provides in response to receiving a packet at a packet processing device having a memory (“on-device memory”), storing the packet at a location in a memory not on the packet processing device (“off-device memory”); creating a packet descriptor corresponding to the packet, the packet descriptor referencing the location; storing the packet descriptor in a packet descriptor queue on the off-device memory; and storing a packet descriptor copy on the on-device memory.
摘要翻译：在一个实施例中，提供了一种方法。该实施例的方法响应于在具有存储器（“在设备存储器”）的分组处理设备处接收分组，将分组存储在不在分组处理设备上的存储器中的位置（“非设备内存” “）; 创建对应于分组的分组描述符，分组描述符引用该位置; 将所述分组描述符存储在所述非设备内存上的分组描述符队列中; 以及将包描述符副本存储在设备上的存储器上。

49. 发明申请

US20070140282A1 Managing on-chip queues in switched fabric networks 审中-公开
标题翻译：管理交换式网络中的片上队列
公开(公告)号：US20070140282A1
公开(公告)日：2007-06-21
申请号：US11315582
申请日：2005-12-21
申请人： Sridhar Lakshmanamurthy , Hugh Wilkinson , Jaroslaw Sydir , Paul Dormitzer
发明人： Sridhar Lakshmanamurthy , Hugh Wilkinson , Jaroslaw Sydir , Paul Dormitzer
IPC分类号： H04L12/56
CPC分类号： H04L47/6255 , H04L47/562 , H04L47/6215 , H04L49/3036 , H04L49/90 , H04L49/9084
摘要： Methods and apparatus, including computer program products, implementing techniques for monitoring a state of a device of a switched fabric network, the device including on-chip queues to store queue descriptors and a data buffer to store data packets, each queue descriptor having a corresponding data packet; detecting a first trigger condition to transition the device from a first state to a second state; and recovering space in the data buffer in response to the first trigger condition detecting, the recovering comprising selecting one or more of the on-chip queues for discard, and removing the data packets corresponding to queue descriptors in the selected one or more on-chip queues from the data buffer.
摘要翻译：包括计算机程序产品的方法和装置，用于监视交换结构网络的设备的状态的实现技术，所述设备包括用于存储队列描述符的片上队列和用于存储数据分组的数据缓冲器，每个队列描述符具有对应的数据包; 检测将所述设备从第一状态转换到第二状态的第一触发条件; 以及响应于所述第一触发条件检测来恢复所述数据缓冲器中的空间，所述恢复包括选择所述片上队列中的一个或多个以进行丢弃，以及移除与所选择的一个或多个片上的队列描述符相对应的数据分组来自数据缓冲区的队列。

50. 发明申请

US20070079073A1 Instruction-assisted cache management for efficient use of cache and memory 有权
标题翻译：指令辅助缓存管理，用于缓存和内存的高效使用
公开(公告)号：US20070079073A1
公开(公告)日：2007-04-05
申请号：US11241538
申请日：2005-09-30
申请人： Mark Rosenbluth , Sridhar Lakshmanamurthy
发明人： Mark Rosenbluth , Sridhar Lakshmanamurthy
IPC分类号： G06F12/00
CPC分类号： G06F9/30047 , G06F12/0804 , G06F12/0888 , G06F12/126
摘要： Instruction-assisted cache management for efficient use of cache and memory. Hints (e.g., modifiers) are added to read and write memory access instructions to identify the memory access is for temporal data. In view of such hints, alternative cache policy and allocation policies are implemented that minimize cache and memory access. Under one policy, a write cache miss may result in a write of data to a partial cache line without a memory read/write cycle to fill the remainder of the line. Under another policy, a read cache miss may result in a read from memory without allocating or writing the read data to a cache line. A cache line soft-lock mechanism is also disclosed, wherein cache lines may be selectably soft locked to indicate preference for keeping those cache lines over non-locked lines.
摘要翻译：指令辅助缓存管理，用于缓存和内存的高效使用。添加提示（例如修饰符）来读取和写入存储器访问指令以识别用于时间数据的存储器访问。鉴于这样的提示，实现了使缓存和存储器访问最小化的替代高速缓存策略和分配策略。在一个策略下，写高速缓存未命中可能导致将数据写入部分高速缓存行而没有存储器读/写周期来填充该行的其余部分。在另一种策略下，读高速缓存未命中可能导致从存储器的读取，而无需将读取的数据分配或写入高速缓存行。还公开了一种高速缓存行软锁定机制，其中高速缓存行可以被可选地软锁定以指示将这些高速缓存行保持在非锁定行上的偏好。

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