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41. 发明授权

US06537893B2 Substrate isolated transistor 有权
公开(公告)号：US06537893B2
公开(公告)日：2003-03-25
申请号：US10194270
申请日：2002-07-11
申请人： Jeffrey T. Watt
发明人： Jeffrey T. Watt
IPC分类号： H01L2176
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493
摘要： A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate.

42. 发明授权

US5477413A ESD protection structure for P-well technology 失效
标题翻译： P-well技术的ESD保护结构
公开(公告)号：US5477413A
公开(公告)日：1995-12-19
申请号：US187746
申请日：1994-01-26
申请人： Jeffrey T. Watt
发明人： Jeffrey T. Watt
IPC分类号： H01L27/02 , H02H9/04
CPC分类号： H01L27/0251
摘要： An ESD protection structure for p-well technology using nMOS FETs that prevents the lock-on condition normally occurring after one FET of a multi finger structure snaps back. The multifinger structure is contained in a main p-well and channels ESDs of a first polarity from the contact pad to a metal conduit. A resistance is provided between the main p-well and the conduit. Further, the circuit channeling ESDs of a polarity opposite to the first polarity is contained in a second p-well that is distinct from the main p-well. An ESD event causes one of the fingers to snap back. Resulting drain current through that finger generates electron hole pairs in the main p-well by impact ionization. Thus generated holes, traveling to the conduit through the resistance, raise the voltage of the main p-well, and therefore shift the i-v characteristic curves of all the FETs to a point where they no longer exhibit a knee. The absence of a knee prevents the remaining fingers from being locked off by the finger that snapped back. Consequently, all FETs are turned on and ESD protection is provided by all FETs in the main p-well.
摘要翻译：使用nMOS FET的p阱技术的ESD保护结构，防止在多指结构的一个FET捕获之后通常发生的锁定状态。多焦点结构包含在主p阱中，并且将从接触垫到金属导管的第一极性的通道ESD。在主p阱和导管之间提供电阻。此外，与第一极性相反的极性的电路通道ESD被包含在与主p阱不同的第二p阱中。 ESD事件导致其中一根手指回弹。通过该手指产生的漏极电流通过冲击电离在主p阱中产生电子空穴对。因此产生的孔通过电阻传导到导管，提高了主p阱的电压，因此将所有FET的i-v特性曲线转移到不再显示膝盖的点。没有膝盖可防止剩余的手指被卡扣的手指锁定。因此，所有FET都导通，ESD保护由主p阱中的所有FET提供。

43. 发明授权

US09305992B2 Integrated circuit inductors with intertwined conductors 有权
标题翻译：具有交织导体的集成电路电感器
公开(公告)号：US09305992B2
公开(公告)日：2016-04-05
申请号：US13161893
申请日：2011-06-16
申请人： Shuxian Chen , Jeffrey T. Watt
发明人： Shuxian Chen , Jeffrey T. Watt
IPC分类号： H01L49/02 , H01L23/522 , H01F17/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0046 , H01F2017/0073 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An inductor may be formed from a conductive path that includes intertwined conductive lines. There may be two, three, or more than three intertwined conductive lines in the conductive path. The conductive lines may be formed from conductive structures in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers that include conductive traces and may include via layers that include vias for interconnecting the traces. The intertwined conductive lines may be formed from the conductive structures in the metal and via layers. In crossover regions, the conductive lines may cross each other without electrically connecting to each other. Vias may be used to couple multiple layers of traces together to reduce line resistance.
摘要翻译：电感器可以由包括相互缠绕的导线的导电路径形成。在导电路径中可能有两个，三个或多于三个相互缠绕的导线。导电线可以由集成电路的电介质堆叠中的导电结构形成。电介质堆叠可以包括包括导电迹线的金属层，并且可以包括通孔层，其包括用于互连迹线的通孔。相互缠绕的导线可以由金属和通孔层中的导电结构形成。在交叉区域中，导线可彼此交叉而不彼此电连接。通孔可用于将多层迹线耦合在一起以降低线路电阻。

44. 发明授权

US09224685B1 Shielded metal-oxide-metal (MOM) capacitor structure 有权
标题翻译：屏蔽金属氧化物金属（MOM）电容器结构
公开(公告)号：US09224685B1
公开(公告)日：2015-12-29
申请号：US13416137
申请日：2012-03-09
申请人： Weiqi Ding , Wilson Wong , Shuxian Chen , Jeffrey T. Watt
发明人： Weiqi Ding , Wilson Wong , Shuxian Chen , Jeffrey T. Watt
IPC分类号： H01L23/522 , H01L49/02
CPC分类号： H01L23/5226 , H01L23/522 , H01L23/5223 , H01L23/5225 , H01L28/82 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： A metal-oxide-metal (MOM) capacitor structure is disclosed. The MOM capacitor includes a plurality of layers, each layer having a plurality of electrodes. The plurality of electrodes, separated by oxide layers, forms a first plate and a second plate of the MOM capacitor. The plurality of electrodes on each of the layers is coupled to a plurality of electrodes on an adjacent layer through a plurality of vias. A shield layer is coupled to each of the electrodes that forms the second plate of the MOM capacitor on each of the plurality of layers.
摘要翻译：公开了一种金属氧化物金属（MOM）电容器结构。 MOM电容器包括多个层，每层具有多个电极。由氧化物层分隔开的多个电极形成MOM电容器的第一板和第二板。每个层上的多个电极通过多个通孔耦合到相邻层上的多个电极。屏蔽层耦合到在多个层中的每一层上形成MOM电容器的第二板的每个电极。

45. 发明授权

US08912605B1 ESD protection circuit 有权
标题翻译： ESD保护电路
公开(公告)号：US08912605B1
公开(公告)日：2014-12-16
申请号：US13538508
申请日：2012-06-29
申请人： Charles Y. Chu , Jeffrey T. Watt
发明人： Charles Y. Chu , Jeffrey T. Watt
IPC分类号： H01L23/62
CPC分类号： H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： A multi-fingered gate transistor formed in a substrate of one conductivity type overlying a well of a second conductivity type. Ohmic contact to the well is made by an implanted region of the second conductivity type that circumscribes the gate transistor. Ohmic contact to the substrate is made by taps located on sides of the gate structure between the gate structure and the well contact. Floating wells are located on opposite sides of the gate structure between the substrate taps and the ends of the gates to isolate these substrate taps and force current flow in the substrate under the gate transistor to be substantially perpendicular to the direction in which the gate fingers extend. This increases the potential difference between these substrate regions and source regions in the gate transistor, thereby aiding the triggering of the parasitic bipolar transistors under adjacent gate fingers into a high current state.
摘要翻译：形成在覆盖第二导电类型的阱的一种导电类型的衬底中的多指栅极晶体管。与阱的欧姆接触由限制栅晶体管的第二导电类型的注入区域制成。通过位于栅极结构和阱接触之间的栅极结构侧面的抽头来形成与衬底的欧姆接触。浮动阱位于栅极结构的相对侧的栅极结构的两侧之间，以隔离这些衬底抽头并迫使栅极晶体管下方的衬底中的电流大致垂直于栅极指延伸的方向。这增加了栅极晶体管中的这些衬底区域和源极区域之间的电势差，从而有助于将相邻栅极指状物处的寄生双极晶体管触发成高电流状态。

46. 发明授权

US08619398B1 ESD protection for differential output pairs 有权
标题翻译：差分输出对的ESD保护
公开(公告)号：US08619398B1
公开(公告)日：2013-12-31
申请号：US13365579
申请日：2012-02-03
申请人： Antonio Gallerano , Charles Y. Chu , Jeffrey T. Watt
发明人： Antonio Gallerano , Charles Y. Chu , Jeffrey T. Watt
IPC分类号： H02H3/22
CPC分类号： H02H3/22
摘要： In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.
摘要翻译：在传统的差分输出电路中，输出端连接到差分对晶体管的漏极，晶体管的源极在第一个节点连接在一起。晶体管的主体连接到具有不同于第一节点的电位的第二节点。在HBM ESD事件发生的情况下，放电可能通过差分晶体管发生，从而导致其中的一个被破坏。为了降低这种放电的可能性，在优选实施例中，提供开关以在感测到ESD事件时将每个差分晶体管的主体连接到第一节点。在替代实施例中，当感测到ESD事件时，提供开关以将第一节点连接到第二节点。

47. 发明授权

US08537523B1 Method and apparatus for implementing a metal capacitor with L-shaped fingers 有权
公开(公告)号：US08537523B1
公开(公告)日：2013-09-17
申请号：US12378115
申请日：2009-02-11
申请人： Shuxian Chen , Jeffrey T. Watt
发明人： Shuxian Chen , Jeffrey T. Watt
IPC分类号： H01G4/005 , H01G4/38
CPC分类号： H01L28/86 , H01G4/005 , H01G4/012 , H01G4/33 , H01G4/35 , H01L23/5223 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A metal capacitor includes a plurality of interconnect segments. A first plurality of L-shaped fingers is driven to a first voltage level by a first interconnect segment. A second plurality of L-shaped fingers is driven to a second voltage level by a second interconnect segment. Each of the L-shaped fingers from a set of the first plurality of L-shaped fingers is adjacent to at least one of the L-shaped fingers from a set of the second plurality of L-shaped fingers.

48. 发明授权

US08519403B1 Angled implantation for deep submicron device optimization 失效
标题翻译：用于深亚微米器件优化的角度植入
公开(公告)号：US08519403B1
公开(公告)日：2013-08-27
申请号：US12931584
申请日：2011-02-04
申请人： Che Ta Hsu , Christopher J. Pass , Dale Ibbotson , Jeffrey T. Watt , Yanzhong Xu
发明人： Che Ta Hsu , Christopher J. Pass , Dale Ibbotson , Jeffrey T. Watt , Yanzhong Xu
IPC分类号： H01L27/108 , H01L29/00 , H01L31/036 , H01L31/112
CPC分类号： H01L21/823807 , H01L21/26586 , H01L29/1083
摘要： A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.
摘要翻译：一种形成亚微米器件的方法包括在包括第一掺杂剂型的多晶硅阱和第二掺杂剂型的栅极的第一区域和包括第二掺杂剂型多晶硅阱的第二区域的第一区域上沉积硬掩模，第一掺杂剂类型的栅极。第一个区域上的硬掩模被去除。执行第一掺杂剂类型的倾斜植入以在第二掺杂剂类型的栅极下形成凹穴。

49. 发明申请

US20120098569A1 HARDENED PROGRAMMABLE DEVICES 有权
公开(公告)号：US20120098569A1
公开(公告)日：2012-04-26
申请号：US13338701
申请日：2011-12-28
申请人： Andy L. Lee , Jeffrey T. Watt
发明人： Andy L. Lee , Jeffrey T. Watt
IPC分类号： H03K19/173
CPC分类号： H03K19/173 , G11C5/005 , H01L27/0207 , H03K19/1736 , H03K19/17784
摘要： Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

50. 发明授权

US08068003B2 Integrated circuits with series-connected inductors 有权
标题翻译：具有串联电感的集成电路
公开(公告)号：US08068003B2
公开(公告)日：2011-11-29
申请号：US12721402
申请日：2010-03-10
申请人： Shuxian Chen , Jeffrey T. Watt
发明人： Shuxian Chen , Jeffrey T. Watt
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F2017/0046 , H01F2017/0086
摘要： An integrated circuit inductor may have upper and lower loop-shaped line portions that are connected in series. The upper and lower portions may have 45° bends that form hexagonal or octagonal loops. Each loop portion may have one or more turns. Intervening metal-free regions of metal routing layers may be formed between the two layers to reduce capacitive coupling. Each loop portion may have sets of two or more metal lines shorted in parallel by vias. The upper and lower loops may be laterally offset or nested to reduce capacitive coupling.
摘要翻译：集成电路电感器可以具有串联连接的上下环形线部分。上部和下部可以具有形成六边形或八边形环的45°弯曲。每个环路部分可以具有一个或多个匝数。可以在两个层之间形成金属布线层的不间断的金属区域，以减少电容耦合。每个环部分可以具有由通孔平行短路的两条或更多条金属线组。上下环可以侧向偏移或嵌套以减小电容耦合。

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