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41. 发明授权

US07921261B2 Reserving a global address space 失效
标题翻译：保留全局地址空间
公开(公告)号：US07921261B2
公开(公告)日：2011-04-05
申请号：US11958668
申请日：2007-12-18
申请人： Robert S. Blackmore , Ramakrishnan Rajamony
发明人： Robert S. Blackmore , Ramakrishnan Rajamony
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/5016 , G06F12/0284 , G06F12/109 , G06F2212/656
摘要： A method of operating a data processing system includes each of multiple tasks within a parallel job executing on multiple nodes of the data processing system issuing a respective system call to request reservation, without allocation of backing storage in physical memory, of a global address space defined by a range of effective addresses as global shared memory accessible to all of the multiple tasks within the parallel job. At least two of the tasks within the parallel job allocate global address spaces including a same effective address.
摘要翻译：一种操作数据处理系统的方法包括在数据处理系统的多个节点上执行的并行作业中的每个，发出相应的系统调用以请求预留，而不在物理存储器中分配备份存储器，以定义全局地址空间通过一系列有效地址作为并行作业内的所有多个任务可访问的全局共享存储器。并行作业中的至少两个任务分配全局地址空间，包括相同的有效地址。

42. 发明授权

US07904590B2 Routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture 失效
标题翻译：通过实现多层全图互连架构的数据处理系统路由信息
公开(公告)号：US07904590B2
公开(公告)日：2011-03-08
申请号：US11845215
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F15/173
CPC分类号： G06F15/17381
摘要： A mechanism is provided for routing information through the data processing system. Data is received at a source processor within a set of processors that is to be transmitted to a destination processor, where the data includes address information. A first determination is performed as to whether the destination processor is within a same processor book as the source processor based on the address information. A second determination is performed as to whether the destination processor is within a same supernode as the source processor based on the address information if the destination processor is not within the same processor book. A routing path is identified for the data based on results of the first determination, the second determination, and one or more routing table data structures. The data is then transmitted from the source processor along the identified routing path toward the destination processor.
摘要翻译：提供了一种通过数据处理系统路由信息的机制。在要发送到目标处理器的一组处理器内的源处理器处接收数据，其中数据包括地址信息。基于地址信息，执行目的地处理器是否在与处理器相同的处理器簿内的第一确定。如果目的地处理器不在相同的处理器书中，则基于地址信息来执行关于目的地处理器是否在与源处理器相同的超级节点内的第二确定。基于第一确定，第二确定和一个或多个路由表数据结构的结果，为数据识别路由路径。然后将数据从源处理器沿着识别的路由路径发送到目的地处理器。

43. 发明申请

US20100115204A1 NON-UNIFORM CACHE ARCHITECTURE (NUCA) 有权
标题翻译：非均匀缓存架构（NUCA）
公开(公告)号：US20100115204A1
公开(公告)日：2010-05-06
申请号：US12264682
申请日：2008-11-04
申请人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Xiaoxia Wu , Lixin Zhang
发明人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Xiaoxia Wu , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0846 , G06F12/0848 , G06F12/123 , G06F2212/225 , G06F2212/271
摘要： In one embodiment, a cache memory includes a cache array including a plurality of entries for caching cache lines of data, where the plurality of entries are distributed between a first region implemented in a first memory technology and a second region implemented in a second memory technology. The cache memory further includes a cache directory of the contents of the cache array and a cache controller that controls operation of the cache memory.
摘要翻译：在一个实施例中，高速缓冲存储器包括高速缓存阵列，其包括用于缓存高速缓存数据行的多个条目，其中多个条目分布在以第一存储器技术实现的第一区域和在第二存储器技术中实现的第二区域之间。高速缓冲存储器还包括高速缓存阵列的内容的高速缓存目录和控制高速缓冲存储器的操作的高速缓存控制器。

44. 发明授权

US07698508B2 System and method for reducing unnecessary cache operations 失效
标题翻译：减少不必要的缓存操作的系统和方法
公开(公告)号：US07698508B2
公开(公告)日：2010-04-13
申请号：US11674960
申请日：2007-02-14
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Evan Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Evan Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译：一种用于数据处理系统中缓存管理的系统和方法。数据处理系统包括处理器和存储器层级。存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

45. 发明申请

US20090153897A1 Method, System and Program Product for Reserving a Global Address Space 失效
标题翻译：保留全球地址空间的方法，系统和程序产品
公开(公告)号：US20090153897A1
公开(公告)日：2009-06-18
申请号：US11958668
申请日：2007-12-18
申请人： Robert S. Blackmore , Ramakrishnan Rajamony
发明人： Robert S. Blackmore , Ramakrishnan Rajamony
IPC分类号： G06F3/12
CPC分类号： G06F9/5016 , G06F12/0284 , G06F12/109 , G06F2212/656
摘要： A method of operating a data processing system includes each of multiple tasks within a parallel job executing on multiple nodes of the data processing system issuing a respective system call to request reservation, without allocation of backing storage in physical memory, of a global address space defined by a range of effective addresses as global shared memory accessible to all of the multiple tasks within the parallel job. At least two of the tasks within the parallel job allocate global address spaces including a same effective address.
摘要翻译：一种操作数据处理系统的方法包括在数据处理系统的多个节点上执行的并行作业中的每个，发出相应的系统调用以请求预留，而不在物理存储器中分配备份存储器，以定义全局地址空间通过一系列有效地址作为并行作业内的所有多个任务可访问的全局共享内存。并行作业中的至少两个任务分配全局地址空间，包括相同的有效地址。

46. 发明申请

US20090064165A1 Method for Hardware Based Dynamic Load Balancing of Message Passing Interface Tasks 失效
标题翻译：基于硬件的消息传递接口任务的动态负载平衡方法
公开(公告)号：US20090064165A1
公开(公告)日：2009-03-05
申请号：US11846119
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46
CPC分类号： G06F9/522 , G06F9/5083
摘要： A method for providing hardware based dynamic load balancing of message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了一种用于提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的方法。提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。

47. 发明申请

US20090064140A1 System and Method for Providing a Fully Non-Blocking Switch in a Supernode of a Multi-Tiered Full-Graph Interconnect Architecture 失效
标题翻译：在多层全图互连架构的超节点中提供完全非阻塞开关的系统和方法
公开(公告)号：US20090064140A1
公开(公告)日：2009-03-05
申请号：US11845211
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： G06F9/46
CPC分类号： G06F9/5061 , G06F15/17356 , G06F2209/5012 , H04L49/15 , H04L49/25
摘要： A method, computer program product, and system are provided for transmitting data from a first processor of a data processing system to a second processor of the data processing system. In one or more switches, a set of virtual channels is created, the one or more switches comprising, for each processor, a corresponding switch in the one or more switches. The data is transmitted from the first processor to the second processor through a path comprising a subset of processors of a set of processors in the data processing system. In each processor of the subset of processors, the data is stored in a virtual channel of a corresponding switch before transmitting the data to a next processor. The virtual channel of the corresponding switch in which the data is stored corresponds to a position of the processor in the path through which the data is transmitted.
摘要翻译：提供了一种方法，计算机程序产品和系统，用于将数据从数据处理系统的第一处理器传送到数据处理系统的第二处理器。在一个或多个交换机中，创建一组虚拟通道，一个或多个交换机为每个处理器包括一个或多个交换机中的相应开关。数据通过包括数据处理系统中的一组处理器的处理器的子集的路径从第一处理器传送到第二处理器。在处理器子集的每个处理器中，在将数据发送到下一个处理器之前，将数据存储在相应开关的虚拟通道中。其中存储数据的相应交换机的虚拟通道对应于处理器在数据发送的路径中的位置。

48. 发明申请

US20090063880A1 System and Method for Providing a High-Speed Message Passing Interface for Barrier Operations in a Multi-Tiered Full-Graph Interconnect Architecture 有权
标题翻译：在多层全图互连架构中提供用于屏障操作的高速消息传递接口的系统和方法
公开(公告)号：US20090063880A1
公开(公告)日：2009-03-05
申请号：US11845225
申请日：2007-08-27
申请人： Lakshminarayana B Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： G06F9/46 , G06F1/32
CPC分类号： G06F9/5088
摘要： A method, computer program product, and system are provided performing a Message Passing Interface (MPI) job. A first processor chip receives a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system. The arrival signals identify when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job. Responsive to receiving the set of arrival signals from the set of processor chips, the first processor chip identifies a fastest processor chip of the set of processor chips whose arrival signal arrived first. An operation of the fastest processor chip is modified based on the identification of the fastest processor chip. The set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system.
摘要翻译：提供了执行消息传递接口（MPI）作业的方法，计算机程序产品和系统。第一处理器芯片从数据处理系统中执行MPI作业的任务的一组处理器芯片接收一组到达信号。到达信号确定处理器芯片何时执行用于同步MPI作业任务的同步操作。响应于从该组处理器芯片接收到一组到达信号，第一处理器芯片标识出到达信号到达第一个处理器芯片集合中最快的处理器芯片。基于最快处理器芯片的识别，修改最快处理器芯片的操作。该组处理器芯片包括位于数据处理系统的相同处理器簿或不同处理器簿之一中的处理器芯片。

49. 发明申请

US20090063816A1 System and Method for Performing Collective Operations Using Software Setup and Partial Software Execution at Leaf Nodes in a Multi-Tiered Full-Graph Interconnect Architecture 失效
标题翻译：使用多层全图互连架构中叶节点的软件设置和部分软件执行进行集体操作的系统和方法
公开(公告)号：US20090063816A1
公开(公告)日：2009-03-05
申请号：US11845224
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F15/17381
摘要： A method, computer program product, and system are provided for performing collective operations. In software executing on a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In software executing on the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
摘要翻译：提供了一种执行集体操作的方法，计算机程序产品和系统。在第一处理器书中在母处理器上执行的软件中，在执行集体操作所需的数据处理系统的相同或不同的处理器簿中确定多个其他处理器，由此建立多个处理器，其包含该父处理器和其他处理器。在在母处理器上执行的软件中，多个处理器在逻辑上被布置为分层结构中的多个节点。基于层次结构将集体操作发送到多个处理器。在母处理器的硬件中，从其他处理器的集体操作的执行中接收到结果，基于接收到的结果生成集合操作的最终结果，并输出最终结果。

50. 发明授权

US07475129B2 Estimating bandwidth of client-ISP link 有权
标题翻译：估计客户端 - ISP链路的带宽
公开(公告)号：US07475129B2
公开(公告)日：2009-01-06
申请号：US10734771
申请日：2003-12-12
申请人： Ramakrishnan Rajamony
发明人： Ramakrishnan Rajamony
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04L61/304 , H04L29/12594 , H04L41/0896 , H04L43/00 , H04L43/0882 , H04L43/50 , H04L61/30
摘要： A method, program, and server for estimating the bandwidth of a network connection between a client and a server includes requesting the server to serve first and second objects back-to-back to the client. The first and second objects are sent to the client. The client determines the time interval between delivery of the first and second objects. The time interval is used, in conjunction with information about the size of the second object, to estimate the bandwidth. The requests for the first and second objects preferably identify the first and second objects with URL's that are unique on the network to prevent the request from being serviced by a file cache. The first and second objects may be transmitted to the client from a content distribution network server that is architecturally close to the client's ISP to improve the reliability of the bandwidth estimation.
摘要翻译：用于估计客户端和服务器之间的网络连接的带宽的方法，程序和服务器包括请求服务器将第一和第二对象反向服务于客户端。第一个和第二个对象被发送到客户端。客户端确定第一个和第二个对象的传递之间的时间间隔。使用时间间隔结合关于第二对象的大小的信息来估计带宽。对第一和第二对象的请求优选地识别具有在网络上唯一的URL的第一和第二对象，以防止该请求由文件高速缓存服务。第一和第二对象可以从架构上靠近客户端的ISP的内容分发网络服务器发送到客户端，以提高带宽估计的可靠性。

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