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41. 发明申请

US20060244013A1 Semiconductor memory and fabrication method for the same 失效
标题翻译：半导体存储器及其制造方法相同
公开(公告)号：US20060244013A1
公开(公告)日：2006-11-02
申请号：US11339483
申请日：2006-01-26
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma
IPC分类号： H01L27/10 , H01L21/82
CPC分类号： H01L27/11517 , G11C16/30 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory includes a plurality of active regions; a plurality of bit line contacts disposed on respective active regions; a plurality of first local lines formed in an island shape and in contact with upper surfaces of the plurality of bit line contacts; a plurality of first via contacts in contact with the upper surfaces of the plurality of first local lines and aligned in a direction parallel to the active regions; a first bit line in contact with one of the plurality of first via contacts and extending in a direction parallel to the active regions; and a plurality of second via contacts arranged above the first via contacts that are not in contact with the first bit line through respective second local lines.
摘要翻译：半导体存储器包括多个有源区; 布置在相应的有源区上的多个位线触点; 形成为岛状且与多个位线接触件的上表面接触的多个第一局部线; 多个第一通孔触点，与所述多个第一局部线的上表面接触并且在与所述有源区域平行的方向上对齐; 与所述多个第一通孔接触中的一个接触并沿平行于所述有源区域的方向延伸的第一位线; 以及多个第二通孔接触件，其布置在第一通孔接触件之上，所述第一通孔接头不通过相应的第二本地线路与第一位线接触。

42. 发明申请

US20060237767A1 Semiconductor device with double barrier film 失效
公开(公告)号：US20060237767A1
公开(公告)日：2006-10-26
申请号：US11447947
申请日：2006-06-07
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L29/76 , H01L21/82
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

43. 发明申请

US20060120159A1 Nonvolatile semiconductor memory and programming method for the same 有权
标题翻译：非易失性半导体存储器和编程方法相同
公开(公告)号：US20060120159A1
公开(公告)日：2006-06-08
申请号：US11337653
申请日：2006-01-24
申请人： Makoto Sakuma , Fumitaka Arai , Riichiro Shirota , Yasuhiko Matsunaga
发明人： Makoto Sakuma , Fumitaka Arai , Riichiro Shirota , Yasuhiko Matsunaga
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.
摘要翻译：半导体存储器具有存储单元矩阵，其包括沿着行方向交替排列的多个第一和第二单元列，每个单元列由多个存储单元晶体管实现，并且外围电路被配置为驱动存储单元矩阵，从存储单元矩阵读取信息。外围电路包括（a）被配置为将第一数据写入第一单元列中的存储单元晶体管的引导程序电路，（b）滞后程序电路，被配置为将第二数据写入第一单元列之后的第二单元列中的存储单元晶体管写入数据，以及（c）被配置为控制第一单元列的存储单元晶体管的阈值电压的变化的电压控制器。

44. 发明授权

US07026684B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07026684B2
公开(公告)日：2006-04-11
申请号：US10940844
申请日：2004-09-15
申请人： Makoto Sakuma , Fumitaka Arai , Yasuhiko Matsunaga
发明人： Makoto Sakuma , Fumitaka Arai , Yasuhiko Matsunaga
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42324 , H01L29/7881
摘要： Floating gates and control gates are alternately arranged on a substrate periodically in a first direction via a gate insulation film. Each floating gate has a first portion whose sectional shape is rectangular, and a second portion which is positioned substantially in a middle portion of the first portion and whose sectional shape is rectangular and whose length in a direction parallel to the first direction is smaller than that of the first portion. Each control gate has a third portion between the second portions of a pair of adjacent floating gates, and a fourth portion positioned between the first portions of a pair of adjacent floating gates. The floating gate and a pair of control gates positioned on opposite sides of the floating gate constitute one memory cell, the adjacent memory cells share the control gate positioned between the memory cells.
摘要翻译：浮栅和控制栅极经由栅极绝缘膜沿第一方向周期性地交替布置在基板上。每个浮动栅极具有截面形状为矩形的第一部分，并且第二部分基本上位于第一部分的中间部分中，并且其截面形状为矩形，并且其在与第一方向平行的方向上的长度小于的第一部分。每个控制栅极具有在一对相邻浮动栅极的第二部分之间的第三部分和位于一对相邻浮动栅极的第一部分之间的第四部分。位于浮动栅极相对侧的浮动栅极和一对控制栅极构成一个存储单元，相邻的存储单元共享位于存储单元之间的控制栅极。

45. 发明申请

US20060065913A1 Semiconductor device with double barrier film 失效
标题翻译：具有双阻挡膜的半导体器件
公开(公告)号：US20060065913A1
公开(公告)日：2006-03-30
申请号：US11001223
申请日：2004-12-02
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L21/82 , H01L29/76
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.
摘要翻译：一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。该装置还包括上接触孔，下接触孔和接触塞。上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。下接触孔的上部具有与沟槽相同的宽度。接触塞设置在上接触孔和下接触孔中。

46. 发明申请

US20060060911A1 Nonvolatile semiconductor memory device having adjacent selection transistors connected together 失效
标题翻译：具有连接在一起的相邻选择晶体管的非易失性半导体存储器件
公开(公告)号：US20060060911A1
公开(公告)日：2006-03-23
申请号：US10988534
申请日：2004-11-16
申请人： Makoto Sakuma , Fumitaka Arai
发明人： Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A semiconductor memory device comprising a semiconductor substrate, a plurality of cell transistors provided on the substrate, a plurality of selection gates provided on the substrate, and element-isolation regions provided between the cell transistors and between the selection gates. Each cell transistor has a floating gate provided on a gate insulating film provided on the substrate, a source and drain provided in the substrate and aligned with the sides of the floating gate, an inter-gate insulating film provided on one side of the floating gate, and a control gate provided on the inter-gate insulating film and laying over the one side of the floating gate. The selection gates are connected by conductive members which are provided on the gate insulating film and embedded in the selection gates.
摘要翻译：一种半导体存储器件，包括半导体衬底，设置在衬底上的多个单元晶体管，设置在衬底上的多个选择栅极以及设置在单元晶体管之间和选择栅极之间的元件隔离区域。每个单元晶体管具有设置在设置在基板上的栅极绝缘膜上的浮置栅极，设置在基板中并与浮置栅极的侧对准的源极和漏极，设置在浮置栅极的一侧的栅极间绝缘膜以及设置在栅极间绝缘膜上并铺设在浮动栅极的一侧上的控制栅极。选择栅极由设置在栅极绝缘膜上并嵌入选择栅极的导电构件连接。

47. 发明授权

US07393747B2 Nonvolatile semiconductor memory and a fabrication method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07393747B2
公开(公告)日：2008-07-01
申请号：US11337001
申请日：2006-01-23
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.
摘要翻译：非易失性半导体存储器包括分别具有浮置栅极，控制栅极和栅极间绝缘膜的多个存储单元晶体管，其分别布置在相应的浮置栅极和相应的控制栅极之间，并沿着列方向展开; 以及沿着行方向以恒定间距部署的器件隔离区域，沿着列方向形成条纹图案。控制栅极沿着行方向连续展开，并且栅极间绝缘膜沿列方向串联并沿行方向以恒定的间距彼此分离。

48. 发明授权

US07335938B2 Nonvolatile semiconductor memory and a fabrication method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07335938B2
公开(公告)日：2008-02-26
申请号：US10971161
申请日：2004-10-25
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L29/72
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.
摘要翻译：非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

49. 发明申请

US20060131638A1 Nonvolatile semiconductor memory and a fabrication method thereof 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20060131638A1
公开(公告)日：2006-06-22
申请号：US11337001
申请日：2006-01-23
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.
摘要翻译：非易失性半导体存储器包括分别具有浮置栅极，控制栅极和栅极间绝缘膜的多个存储单元晶体管，其分别布置在相应的浮置栅极和相应的控制栅极之间，并沿着列方向展开; 以及沿着行方向以恒定间距部署的器件隔离区域，沿着列方向形成条纹图案。控制栅极沿着行方向连续展开，并且栅极间绝缘膜沿列方向串联并沿行方向以恒定的间距彼此分离。

50. 发明申请

US20050199938A1 Nonvolatile semiconductor memory and a fabrication method for the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050199938A1
公开(公告)日：2005-09-15
申请号：US10971161
申请日：2004-10-25
申请人： Makoto Sakuma , Atsuhiro Sato
发明人： Makoto Sakuma , Atsuhiro Sato
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.
摘要翻译：非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

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