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41. 发明授权

US06487697B1 Distribution dependent clustering in buffer insertion of high fanout nets 有权
标题翻译：在高扇出网络的缓冲区插入中的分布依赖聚类
公开(公告)号：US06487697B1
公开(公告)日：2002-11-26
申请号：US09820059
申请日：2001-03-28
申请人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykh
发明人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykh
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： Methods and apparatus are disclosed for inserting buffers into the design of an integrated circuit with a high fanout net. If a net has a ramptime violation, all of the driven elements in the net are clustered in such a manner that the total load (capacitance) of the driver decreases. Clustering is based upon a two-dimensional partitioning approach together with three proposed heuristics (expand, shrink and merge), which iteratively partitions the placement regions of the net such that the number of buffers to be inserted and the level of inserted buffer tree are minimized. After clustering, one buffer is inserted for each cluster created in the clustering operation. Each of the inserted buffers drives its corresponding cluster. The buffers that are inserted will not have any ramptime violation, which ensures converge of the buffer insertion scheme. Therefore, each insertion of a level of buffers reduces the overall ramptime of the net. After insertion of a level of buffers, the ramptime of the net is checked once again. If it is still not acceptable, the aforementioned clustering and insertion are repeated and the above cycle is iterated until there is no ramptime violation. During the first iteration of clustering and buffer insertion, the original circuit elements are clustered. After the first iteration of clustering and buffer insertion, the driven elements that are clustered are the buffers that were inserted in the previous iteration. In this manner, levels of buffers may be inserted into the net.
摘要翻译：公开了用于将缓冲器插入到具有高扇出网络的集成电路的设计中的方法和装置。如果一个网络具有呃违反时间，则网络中的所有被驱动元素都会以驱动器的总负载（电容）减小的方式聚集。聚类基于二维分割方法以及三个提出的启发式（扩展，收缩和合并），其迭代地分割网络的放置区域，使得要插入的缓冲器的数量和插入的缓冲器树的级别被最小化。聚类后，为在集群操作中创建的每个集群插入一个缓冲区。每个插入的缓冲区驱动其对应的集群。插入的缓冲区将不会有任何ramptime违规，这确保缓冲区插入方案的收敛。因此，每次插入一级缓冲区可以减少网络的总体上网时间。在插入一级缓冲区后，再次检查网络的启动时间。如果仍然不能接受，则重复前述的聚类和插入，并重复上述循环，直到没有突发性违反。在集群和缓冲区插入的第一次迭代期间，原始电路元件被聚集。在集群和缓冲区插入的第一次迭代之后，聚集的被驱动元素是在先前迭代中插入的缓冲区。以这种方式，可以将缓冲器的级别插入到网中。

42. 发明授权

US07356785B2 Optimizing IC clock structures by minimizing clock uncertainty 失效
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US07356785B2
公开(公告)日：2008-04-08
申请号：US11402146
申请日：2006-04-11
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G01R31/3016
摘要： A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.
摘要翻译：提供了一种用于优化具有由驱动器引脚限定的根和由驱动引脚限定的多个叶片的树形式的时钟网络的过程。该过程包括将第一缓冲区强制到多个叶片的重心，插入一组第二缓冲器，使得每个叶片被插入的缓冲器驱动而没有定时违反，并且将第一缓冲器移动到集合的重心的第二缓冲区。

43. 发明申请

US20060190901A1 Method of buffer insertion to achieve pin specific delays 有权
标题翻译：缓冲区插入方式来实现引脚特定的延迟
公开(公告)号：US20060190901A1
公开(公告)日：2006-08-24
申请号：US11041489
申请日：2005-01-24
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.
摘要翻译：一种用于集成电路设计中的树形网络的缓冲器插入方法包括以下步骤：（a）接收作为输入的包括树形网络的集成电路设计; （b）从单元库选择可用于集成电路设计的缓冲器类型，其导致预定导线长度的最小总延迟; （c）识别树网络中具有所需针特定目标延迟的候选叶节点; （d）在由候选叶节点到树网络的根节点的路径穿过的每个内部节点之间插入缓冲器，并且不是候选叶节点的每个叶节点; （e）从由候选叶节点到树网络的根节点的路径遍历的每个内部节点的上游内部节点在树形网络中创建缓冲器子树; 将通过从候选叶节点到树树网络的根节点的路径遍历的每个内部节点重新编入缓冲器子树中的新缓冲器; 和（g）产生包括缓冲器子树的经修订的集成电路设计的输出。

44. 发明授权

US07096442B2 Optimizing IC clock structures by minimizing clock uncertainty 有权
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US07096442B2
公开(公告)日：2006-08-22
申请号：US10616623
申请日：2003-07-10
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F1/10 , G01R31/3016
摘要： Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined characteristic along the first path. A second path from the launching cell toward the clock source is back-traced to a common one of the marked cells having the predetermined characteristic. Clock uncertainty is calculated based on the portion of the first path from the common marked cell having the predetermined characteristic to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.
摘要翻译：通过从接收小区向时钟源的后向跟踪第一路径并且沿着第一路径标记具有预定特性的每个小区来估计接收小区和网络的启动小区之间的时钟不确定性。从发射单元朝向时钟源的第二路径被追溯到具有预定特性的标记单元中的共同的一个。基于从具有预定特征的公共标记小区到接收小区的第一路径的部分来计算时钟不确定性。如果松弛不超过余量值，则计算时钟不确定度。在一个实施例中，通过将第一缓冲器强制为具有网络的多个缓冲器的重心而没有定时违反来最大化从根到强制缓冲器的公共路径，使得最小化从强制缓冲区到叶片的非公共路径，从而最小化时钟不确定性。

45. 发明授权

US06810515B2 Process of restructuring logics in ICs for setup and hold time optimization 失效
标题翻译：在IC中重组逻辑的过程进行设置和保持时间优化
公开(公告)号：US06810515B2
公开(公告)日：2004-10-26
申请号：US10254380
申请日：2002-09-25
申请人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykh , Elyar E. Gasanov
发明人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykh , Elyar E. Gasanov
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A process of optimizing setup and hold time violations comprising resynthesis of data and clock logics coupled to pins of the integrated circuit to optimize setup time violations, and resynthesizing data and clock logics coupled to pins of the integrated circuit to optimize hold time violations. Optimization of setup time violations is performed by resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations, then resynthesis of the data logics of each pin having a setup time violation to optimize the setup time violations, and then resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations. The hold time violations are then optimized by resynthesizing the data logics to optimize the hold time violations, and then resynthesizing the clock logics to optimize the hold time violations. Cost functions are calculated for each pin based on setup and hold time violations, and are selectively applied to the resynthesis steps.
摘要翻译：优化建立和保持时间冲突的过程，包括耦合到集成电路的引脚的数据和时钟逻辑的合成，以优化建立时间违规，以及重新合并耦合到集成电路引脚的数据和时钟逻辑，以优化保持时间违规。通过重新合成具有建立时间违规的每个引脚的时钟逻辑来优化建立时间违规，优化建立时间违规，然后重新合成具有建立时间违规的每个引脚的数据逻辑，以优化建立时间违规，以及然后重新合成具有设置时间违规的每个引脚的时钟逻辑，以优化设置时间违例。然后通过重新合并数据逻辑来优化保持时间违规，然后重新合成时钟逻辑以优化保持时间违规来优化保持时间违规。根据建立和保持时间违规计算每个引脚的成本函数，并选择性地应用于再合成步骤。

46. 发明授权

US06550045B1 Changing clock delays in an integrated circuit for skew optimization 有权
标题翻译：改变用于偏移优化的集成电路中的时钟延迟
公开(公告)号：US06550045B1
公开(公告)日：2003-04-15
申请号：US09991574
申请日：2001-11-20
申请人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykj , Elyar E. Gasanov
发明人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykj , Elyar E. Gasanov
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： Clock delays are changed in a clock network of an ASIC. Global skew optimization is achieved by restructuring a clock domain to balance clock delays in the domain, and by equalizing clock delays of several domains of a group that have timing paths between them. Clock delays are equalized using buffer chains affecting all leaves of the respective domain, and an additional delay coefficient that equalizes clock delay. The clock insertion delays are changed for each group by restructuring the buffers in the group, based on both the data and clock logics to optimize the paths. Local skew optimization is achieved by restructuring the clock domain using a heuristic algorithm and re-ordering the buffers of the domain. A computer program enables a processor to carry out the processes.
摘要翻译：时钟延迟在ASIC的时钟网络中发生变化。通过重构时钟域来平衡域中的时钟延迟并通过均衡具有时间路径的组的几个域的时钟延迟来实现全局偏移优化。使用影响相应域的所有叶片的缓冲器链和延迟时间相等的附加延迟系数来均衡时钟延迟。基于数据和时钟逻辑，通过重组组中的缓冲区来为每个组改变时钟插入延迟，以优化路径。局部偏移优化是通过使用启发式算法重构时钟域并重新排序域缓冲来实现的。计算机程序使得处理器能够执行这些处理。

47. 发明授权

US06463572B1 IC timing analysis with known false paths 有权
标题翻译：具有已知虚路径的IC时序分析
公开(公告)号：US06463572B1
公开(公告)日：2002-10-08
申请号：US09871129
申请日：2001-05-31
申请人： Ivan Pavisic , Pedja Raspopovic , Aiguo Lu
发明人： Ivan Pavisic , Pedja Raspopovic , Aiguo Lu
IPC分类号： G06F945
CPC分类号： G06F17/5031
摘要： True paths are identified in a timing graph of a circuit in which the timing graph contains known false paths containing nodes of at least two sets selected from FROM, THROUGH and TO nodes. The false paths are processed to include sets of FROM and TO nodes and then transformed into equivalent sets of two logical false paths. True path intervals are constructed as logical subgraphs that do not describe any equivalent false path. In preferred embodiments, the process is carried out by a computer under control of a computer readable program.
摘要翻译：真实路径在电路的时序图中被识别，其中定时图包含包含从FROM，THROUGH和TO节点中选择的至少两个集合的节点的已知虚路径。处理伪路径以包括FROM和TO节点的集合，然后转换成两个逻辑假路径的等效集合。真实路径间隔被构造为不描述任何等效假路径的逻辑子图。在优选实施例中，该过程由计算机在计算机可读程序的控制下执行。

48. 发明授权

US07546505B2 Built in self test transport controller architecture 失效
标题翻译：内置自检传输控制器架构
公开(公告)号：US07546505B2
公开(公告)日：2009-06-09
申请号：US11557513
申请日：2006-11-08
申请人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
发明人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/16 , G11C29/34 , G11C2029/0401 , G11C2029/1204 , G11C2029/2602
摘要： A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive results. Transport controllers are paired with the columns of memory cells. The controllers receive commands from the memory test controller, test memory cells within the column, receive test results, and provide the results to the memory test controller. The transport controllers operate in three modes. A production testing mode tests the memory cells in different columns, accumulating the results for a given column with the controller associated with the column. A production testing mode retrieves the results from the controllers. A diagnostic testing mode tests memory cells within one column, while retrieving results for the column.
摘要翻译：内存自检电路在内存矩阵中。矩阵内的存储单元被排列成列。该电路只有一个内存测试控制器，适用于启动命令并接收结果。传输控制器与存储单元的列配对。控制器从存储器测试控制器接收命令，测试列内的测试存储单元，接收测试结果，并将结果提供给存储器测试控制器。运输控制器以三种模式运行。生产测试模式测试不同列中的存储单元，使用与列相关联的控制器累积给定列的结果。生产测试模式从控制器检索结果。诊断测试模式测试一列内的存储单元，同时检索列的结果。

49. 发明授权

US06757877B2 System and method for identifying and eliminating bottlenecks in integrated circuit designs 失效
标题翻译：识别和消除集成电路设计瓶颈的系统和方法
公开(公告)号：US06757877B2
公开(公告)日：2004-06-29
申请号：US10083411
申请日：2002-02-27
申请人： Robert Stenberg , Ivan Pavisic
发明人： Robert Stenberg , Ivan Pavisic
IPC分类号： G06F1750
CPC分类号： G06F17/5031 , G06F17/5068
摘要： A method of integrated circuit design and a circuit design tool. Critical paths are identified in an integrated circuit design. Identified edges are weighted. Edges are assigned a higher weight responsive to the number of critical paths in which they are included. A net criticality is assigned to each weighted edge based upon the edge's weight. Cells are re-placed and wired according to net criticality.
摘要翻译：一种集成电路设计方法和电路设计工具。集成电路设计中确定了关键路径。识别的边被加权。响应于包括它们的关键路径的数量，边缘被赋予更高的权重。基于边缘权重，将每个加权边缘分配净关键度。细胞根据净临界值重新放置和布线。

50. 发明授权

US07667494B2 Methods and apparatus for fast unbalanced pipeline architecture 有权
标题翻译：快速不平衡管道架构的方法与装置
公开(公告)号：US07667494B2
公开(公告)日：2010-02-23
申请号：US12058881
申请日：2008-03-31
申请人： Alexander Andreev , Ivan Pavisic , Igor Vikhliantsev
发明人： Alexander Andreev , Ivan Pavisic , Igor Vikhliantsev
IPC分类号： G11C19/00 , H03K19/173
CPC分类号： G11C19/00 , G06F9/3869 , Y10T29/49002
摘要： Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time.
摘要翻译：为快速不平衡管道架构提供了方法和装置。公开的流水线缓冲器包括串联连接的多个存储器寄存器，多个存储器寄存器中的每一个，诸如触发器，具有使能输入和时钟输入; 以及控制存储器寄存器，其具有驱动多个存储器寄存器的使能输入的输出，由此控制存储器寄存器的输入上的预定二进制值在下一个时钟周期上移位多个存储器寄存器的值。多个公开的管道自助餐可以被配置为多级配置。多个存储寄存器中的至少一个可以包括同步流水线缓冲器的锁存储寄存器。流水线缓冲器可以可选地包括延迟门以延迟时钟信号和反相器以反转延迟的时钟信号。时钟信号可以由延迟门延迟，使得流水线缓冲器的输出在正确的时间被施加到流水线缓冲器的下一级。

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