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1. 发明申请

US20060190886A1 Optimizing IC clock structures by minimizing clock uncertainty 失效
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US20060190886A1
公开(公告)日：2006-08-24
申请号：US11402146
申请日：2006-04-11
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G01R31/3016
摘要： A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.
摘要翻译：提供了一种用于优化具有由驱动器引脚限定的根和由驱动引脚限定的多个叶的树形式的时钟网的过程。该过程包括将第一缓冲区强制到多个叶片的重心，插入一组第二缓冲器，使得每个叶片被插入的缓冲器驱动而没有定时违反，并且将第一缓冲器移动到该集合的重心的第二缓冲区。

2. 发明申请

US20050010884A1 Optimizing IC clock structures by minimizing clock uncertainty 有权
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US20050010884A1
公开(公告)日：2005-01-13
申请号：US10616623
申请日：2003-07-10
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G01R31/30 , G06F1/10 , G06F9/45
CPC分类号： G06F1/10 , G01R31/3016
摘要： Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined character along the first path. A second path from the launching cell toward the clock source is back-traced to a predetermined marked cell. Clock uncertainty is calculated based on the portion of the first path from the predetermined marked cell to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.
摘要翻译：通过从接收单元向时钟源的后向跟踪第一路径并且沿着第一路径标记具有预定字符的每个单元来估计接收小区和网络的启动小区之间的时钟不确定性。从启动单元向时钟源的第二条路径被追溯到预定的标记单元。基于从预定标记小区到接收小区的第一路径的部分来计算时钟不确定性。如果松弛不超过余量值，则计算时钟不确定度。在一个实施例中，通过将第一缓冲器强制为具有网络的多个缓冲器的重心而没有定时违反来最大化从根到强制缓冲器的公共路径，使得最小化从强制缓冲区到叶片的非公共路径，从而最小化时钟不确定性。

3. 发明授权

US07243324B2 Method of buffer insertion to achieve pin specific delays 有权
标题翻译：缓冲区插入方式来实现引脚特定的延迟
公开(公告)号：US07243324B2
公开(公告)日：2007-07-10
申请号：US11041489
申请日：2005-01-24
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.
摘要翻译：一种用于集成电路设计中的树形网络的缓冲器插入方法包括以下步骤：（a）接收作为输入的包括树形网络的集成电路设计; （b）从单元库选择可用于集成电路设计的缓冲器类型，其导致预定导线长度的最小总延迟; （c）识别树网络中具有所需针特定目标延迟的候选叶节点; （d）在由候选叶节点到树网络的根节点的路径穿过的每个内部节点之间插入缓冲器，并且不是候选叶节点的每个叶节点; （e）从由候选叶节点到树网络的根节点的路径遍历的每个内部节点的上游内部节点在树形网络中创建缓冲器子树; 将通过从候选叶节点到树树网络的根节点的路径遍历的每个内部节点重新编入缓冲器子树中的新缓冲器; 和（g）产生包括缓冲器子树的经修订的集成电路设计的输出。

4. 发明授权

US07356785B2 Optimizing IC clock structures by minimizing clock uncertainty 失效
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US07356785B2
公开(公告)日：2008-04-08
申请号：US11402146
申请日：2006-04-11
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G01R31/3016
摘要： A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.
摘要翻译：提供了一种用于优化具有由驱动器引脚限定的根和由驱动引脚限定的多个叶片的树形式的时钟网络的过程。该过程包括将第一缓冲区强制到多个叶片的重心，插入一组第二缓冲器，使得每个叶片被插入的缓冲器驱动而没有定时违反，并且将第一缓冲器移动到集合的重心的第二缓冲区。

5. 发明申请

US20060190901A1 Method of buffer insertion to achieve pin specific delays 有权
标题翻译：缓冲区插入方式来实现引脚特定的延迟
公开(公告)号：US20060190901A1
公开(公告)日：2006-08-24
申请号：US11041489
申请日：2005-01-24
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.
摘要翻译：一种用于集成电路设计中的树形网络的缓冲器插入方法包括以下步骤：（a）接收作为输入的包括树形网络的集成电路设计; （b）从单元库选择可用于集成电路设计的缓冲器类型，其导致预定导线长度的最小总延迟; （c）识别树网络中具有所需针特定目标延迟的候选叶节点; （d）在由候选叶节点到树网络的根节点的路径穿过的每个内部节点之间插入缓冲器，并且不是候选叶节点的每个叶节点; （e）从由候选叶节点到树网络的根节点的路径遍历的每个内部节点的上游内部节点在树形网络中创建缓冲器子树; 将通过从候选叶节点到树树网络的根节点的路径遍历的每个内部节点重新编入缓冲器子树中的新缓冲器; 和（g）产生包括缓冲器子树的经修订的集成电路设计的输出。

6. 发明授权

US07096442B2 Optimizing IC clock structures by minimizing clock uncertainty 有权
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US07096442B2
公开(公告)日：2006-08-22
申请号：US10616623
申请日：2003-07-10
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F1/10 , G01R31/3016
摘要： Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined characteristic along the first path. A second path from the launching cell toward the clock source is back-traced to a common one of the marked cells having the predetermined characteristic. Clock uncertainty is calculated based on the portion of the first path from the common marked cell having the predetermined characteristic to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.
摘要翻译：通过从接收小区向时钟源的后向跟踪第一路径并且沿着第一路径标记具有预定特性的每个小区来估计接收小区和网络的启动小区之间的时钟不确定性。从发射单元朝向时钟源的第二路径被追溯到具有预定特性的标记单元中的共同的一个。基于从具有预定特征的公共标记小区到接收小区的第一路径的部分来计算时钟不确定性。如果松弛不超过余量值，则计算时钟不确定度。在一个实施例中，通过将第一缓冲器强制为具有网络的多个缓冲器的重心而没有定时违反来最大化从根到强制缓冲器的公共路径，使得最小化从强制缓冲区到叶片的非公共路径，从而最小化时钟不确定性。

7. 发明授权

US08359466B2 Security association prefetch for security protcol processing 有权
标题翻译：安全关联预取用于安全性质的处理
公开(公告)号：US08359466B2
公开(公告)日：2013-01-22
申请号：US13097213
申请日：2011-04-29
申请人： Sheng Liu , Nikola Radovanovic , Ephrem Wu
发明人： Sheng Liu , Nikola Radovanovic , Ephrem Wu
IPC分类号： H04L29/06 , G06F9/00
CPC分类号： H04L63/0485 , H04L63/164 , H04L63/20 , H04L69/12 , H04L69/32
摘要： Described embodiments provide a network processor that includes a security protocol processor for staged security processing of a packet having a security association (SA). An SA request module computes an address for the SA. The SA is fetched to a local memory. An SA prefetch control word (SPCW) is read from the SA in the local memory. The SPCW identifies one or more regions of the SA and the associated stages for the one or more regions. An SPCW parser generates one or more stage SPCWs (SSPCWs) from the SPCW. Each of the SSPCWs is stored in a corresponding SSPCW register. A prefetch module services each SSPCW register in accordance with a predefined algorithm. The prefetch module fetches a requested SA region and provides the requested SA region to a corresponding stage for the staged security processing of an associated portion of the packet.
摘要翻译：描述的实施例提供一种网络处理器，其包括用于具有安全关联（SA）的分组的分级安全处理的安全协议处理器。 SA请求模块计算SA的地址。 SA被提取到本地内存。从本地存储器中的SA读取SA预取控制字（SPCW）。 SPCW识别SA的一个或多个区域以及一个或多个区域的相关联的阶段。 SPCW解析器从SPCW生成一个或多个阶段SPCW（SSPCW）。每个SSPCW存储在相应的SSPCW寄存器中。预取模块根据预定义的算法为每个SSPCW寄存器提供服务。预取模块读取所请求的SA区域，并将所请求的SA区域提供给相应阶段，用于分组的相关部分的分段安全处理。

8. 发明授权

US07082561B2 Built-in functional tester for search engines 失效
公开(公告)号：US07082561B2
公开(公告)日：2006-07-25
申请号：US10135624
申请日：2002-04-30
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Nikola Radovanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Nikola Radovanovic
IPC分类号： G01R31/28
CPC分类号： G01R31/3183 , G01R31/318378
摘要： A search engine apparatus having a built-in functional test may include an input generator, a search engine, a pseudo search engine and a comparator. The inputs generator is suitable for generating outputs including commands and points associated with the commands. The search engine and the pseudo search engine are communicatively coupled to the inputs generator. The search engine suitable for performing search and edit operations and the pseudo search engine is suitable for simulating the search engine by generating pseudo search engine outputs. The comparator is communicatively coupled to the search engine and the pseudo search engine, and is suitable for comparing outputs received from the search engine and pseudo search engine.

9. 发明授权

US08438641B2 Security protocol processing for anti-replay protection 失效
标题翻译：用于防重放保护的安全协议处理
公开(公告)号：US08438641B2
公开(公告)日：2013-05-07
申请号：US12980489
申请日：2010-12-29
申请人： Vojislav Vukovic , Brian Vanderwarn , Nikola Radovanovic , Ephrem Wu
发明人： Vojislav Vukovic , Brian Vanderwarn , Nikola Radovanovic , Ephrem Wu
IPC分类号： G06F7/04
CPC分类号： H04L63/1466
摘要： Described embodiments provide a network processor that includes a security protocol processor to prevent replay attacks on the network processor. A memory stores security associations for anti-replay operations. A pre-fetch module retrieves an anti-replay window corresponding to a data stream of the network processor. The anti-replay window has a range of sequence numbers. When the network processor receives a data packet, the security hardware accelerator determines a value of the received sequence number with respect to minimum and maximum values of a sequence number range of the anti-replay window. Depending on the value, the data packet is either received or accepted. The anti-replay window might be updated to reflect the receipt of the most recent data packet.
摘要翻译：所描述的实施例提供一种包括安全协议处理器以防止对网络处理器的重放攻击的网络处理器。内存存储用于反重放操作的安全关联。预取模块检索对应于网络处理器的数据流的反重播窗口。反播放窗口具有一系列序列号。当网络处理器接收到数据分组时，安全硬件加速器相对于反重放窗口的序列号范围的最小值和最大值确定接收到的序列号的值。取决于值，数据包被接收或接受。可以更新反重播窗口以反映最近的数据包的接收。

10. 发明申请

US20120278615A1 SECURTIY ASSOCIATION PREFETCH FOR SECURITY PROTCOL PROCESSING 有权
标题翻译：安全机构处理安全协会
公开(公告)号：US20120278615A1
公开(公告)日：2012-11-01
申请号：US13097213
申请日：2011-04-29
申请人： Sheng Liu , Nikola Radovanovic , Ephrem Wu
发明人： Sheng Liu , Nikola Radovanovic , Ephrem Wu
IPC分类号： H04L29/06
CPC分类号： H04L63/0485 , H04L63/164 , H04L63/20 , H04L69/12 , H04L69/32
摘要： Described embodiments provide a network processor that includes a security protocol processor for staged security processing of a packet having a security association (SA). An SA request module computes an address for the SA. The SA is fetched to a local memory. An SA prefetch control word (SPCW) is read from the SA in the local memory. The SPCW identifies one or more regions of the SA and the associated stages for the one or more regions. An SPCW parser generates one or more stage SPCWs (SSPCWs) from the SPCW. Each of the SSPCWs is stored in a corresponding SSPCW register. A prefetch module services each SSPCW register in accordance with a predefined algorithm. The prefetch module fetches a requested SA region and provides the requested SA region to a corresponding stage for the staged security processing of an associated portion of the packet.
摘要翻译：描述的实施例提供一种网络处理器，其包括用于具有安全关联（SA）的分组的分级安全处理的安全协议处理器。 SA请求模块计算SA的地址。 SA被提取到本地内存。从本地存储器中的SA读取SA预取控制字（SPCW）。 SPCW识别SA的一个或多个区域以及一个或多个区域的相关联的阶段。 SPCW解析器从SPCW生成一个或多个阶段SPCW（SSPCW）。每个SSPCW存储在相应的SSPCW寄存器中。预取模块根据预定义的算法为每个SSPCW寄存器提供服务。预取模块读取所请求的SA区域，并将所请求的SA区域提供给相应阶段，用于分组的相关部分的分段安全处理。

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