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41. 发明申请

US20050051847A1 Semiconductor input protection circuit 失效
公开(公告)号：US20050051847A1
公开(公告)日：2005-03-10
申请号：US10968685
申请日：2004-10-19
申请人： Nobuaki Tsuji , Masao Noro , Terumitsu Maeno , Seiji Hirade
发明人： Nobuaki Tsuji , Masao Noro , Terumitsu Maeno , Seiji Hirade
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/06 , H01L27/092 , H01L29/74
CPC分类号： H01L27/0255 , H01L27/0259 , H01L27/0288
摘要： A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of −2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

42. 发明授权

US06847059B2 Semiconductor input protection circuit 有权
标题翻译：半导体输入保护电路
公开(公告)号：US06847059B2
公开(公告)日：2005-01-25
申请号：US09982335
申请日：2001-10-18
申请人： Nobuaki Tsuji , Masao Noro , Terumitsu Maeno , Seiji Hirade
发明人： Nobuaki Tsuji , Masao Noro , Terumitsu Maeno , Seiji Hirade
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/06 , H01L27/092 , H01L29/74 , H01L23/62
CPC分类号： H01L27/0255 , H01L27/0259 , H01L27/0288
摘要： A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of −2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.
摘要翻译：横向PNP晶体管PB和横向NPN晶体管NB串联连接在输入端子和参考电位（地电位）之间。在晶体管PB中形成二极管D1。在晶体管NB中，形成二极管D3。当输入+2000V的ESD时，晶体管NB导通，而当输入-2000V的ESD时，晶体管PB导通。能够输入的正信号的电平受到二极管D3的反向击穿电压（例如，18至50V）的限制，而能够被输入的负信号的电平受到反向击穿电压的限制（例如，，13〜15V）。

43. 发明授权

US06826215B2 Laser diode driving circuit 失效
标题翻译：激光二极管驱动电路
公开(公告)号：US06826215B2
公开(公告)日：2004-11-30
申请号：US09789975
申请日：2001-02-21
申请人： Nobuaki Tsuji , Kunito Takahashi
发明人： Nobuaki Tsuji , Kunito Takahashi
IPC分类号： H01S313
CPC分类号： H01S5/042 , H01S5/0428
摘要： A laser diode driving circuit is provided, which is capable of supplying a laser diode thereof with a high-speed pulse current. A current source supplies a current to the laser diode. An NMOS transistor as a first switch is connected between the current source and the laser diode. An NMOS transistor as a second switch is connected between a junction between the current source and the first switch and a pseudo load. A controller supplies a first voltage pulse signal to the first switch and a second voltage pulse signal opposite in phase to the first voltage pulse signal to the second switch to switch the first and second switches in a complementary manner.
摘要翻译：提供一种能够向其激光二极管提供高速脉冲电流的激光二极管驱动电路。电流源向激光二极管提供电流。作为第一开关的NMOS晶体管连接在电流源和激光二极管之间。作为第二开关的NMOS晶体管连接在电流源和第一开关之间的连接点和伪负载之间。控制器向第一开关提供第一电压脉冲信号和与第一电压脉冲信号相位相反的第二电压脉冲信号到第二开关以互补的方式切换第一和第二开关。

44. 发明授权

US5391920A Semiconductor device having peripheral metal wiring 失效
标题翻译：具有外围金属布线的半导体器件
公开(公告)号：US5391920A
公开(公告)日：1995-02-21
申请号：US910624
申请日：1992-07-08
申请人： Nobuaki Tsuji
发明人： Nobuaki Tsuji
IPC分类号： H01L23/528 , H01L23/485 , H01L29/40
CPC分类号： H01L23/528 , H01L2924/0002 , Y10S257/92
摘要： At a peripheral area of a semiconductor chip where active elements are not formed, a layer underlying a power supply wiring or ground wiring is provided with an uneven surface. The uneven or corrugated surface at the interface between the wiring and the underlying layer makes the wiring unsusceptible to slide. The uneven surface can be realized by interposing foreign matters between insulating layers, by selectively reducing the thickness of an insulating layer, or by forming openings in an insulating layer.
摘要翻译：在没有形成有源元件的半导体芯片的周边区域，电源布线或接地布线下方的层设置有不平坦的表面。在布线和下层之间的界面处的不平坦或波纹表面使得布线不能滑动。可以通过在绝缘层之间插入异物，通过选择性地减小绝缘层的厚度，或者通过在绝缘层中形成开口来实现不平坦表面。

45. 发明授权

US5231656A Device for detecting film information 失效
标题翻译：用于检测电影信息的设备
公开(公告)号：US5231656A
公开(公告)日：1993-07-27
申请号：US750593
申请日：1991-08-28
申请人： Haruhiko Sakuma , Nobuaki Tsuji
发明人： Haruhiko Sakuma , Nobuaki Tsuji
IPC分类号： G03B7/24 , G03B27/52 , G03B42/02 , G03C1/00 , G03C3/00 , G03C5/16 , G03C11/02 , G03D13/00
CPC分类号： G03D13/007 , G03B27/521 , G03B42/02 , G03C11/02
摘要： A film information detecting method for detecting information provided on a film for photography and a device for practicing the same. The film information detecting method includes the steps of irradiating a film information display portion on the film for photography with a light to which the film is not sensitive and detecting the film information. The film information detecting device for detecting information provided on a film for photography includes a light irradiation device for irradiating an information display portion with a light to which the film is not sensitive and a film information detecting device for detecting film information displayed by the film information display portion.

46. 发明授权

US08653803B2 Voltage generation circuit 有权
标题翻译：电压发生电路
公开(公告)号：US08653803B2
公开(公告)日：2014-02-18
申请号：US13200214
申请日：2011-09-21
申请人： Norihiro Kawagishi , Nobuaki Tsuji , Toshio Maejima
发明人： Norihiro Kawagishi , Nobuaki Tsuji , Toshio Maejima
IPC分类号： G05F1/565 , G05F1/618
CPC分类号： H02M3/156 , H02M2001/0032 , Y02B70/16
摘要： A voltage generation circuit includes a voltage detection circuit that generates a detection voltage according to an output voltage, a reference voltage generation circuit that generates a reference voltage which changes periodically, a comparison circuit that generates a control signal according to a result of a comparison between the detection voltage and the reference voltage, wherein control pulses each having a pulse width according to the detection voltage are sequentially appeared in the control signal, and a driving pulse generation circuit that generates a driving pulse corresponding to the control pulse and supplies the generated driving pulse to a transistor connected to a DC power source when the pulse width of the control pulse exceeds a predetermined width, and stops generating the driving pulse when the pulse width of the control pulse becomes smaller than the predetermined width.
摘要翻译：电压产生电路包括产生根据输出电压的检测电压的电压检测电路，产生周期性变化的参考电压的基准电压产生电路，根据比较结果产生控制信号的比较电路检测电压和参考电压，其中在控制信号中顺序出现各自具有根据检测电压的脉冲宽度的控制脉冲，以及驱动脉冲产生电路，其产生与控制脉冲相对应的驱动脉冲并提供所产生的驱动当控制脉冲的脉冲宽度超过预定宽度时，连接到直流电源的晶体管脉冲，并且当控制脉冲的脉冲宽度变得小于预定宽度时停止产生驱动脉冲。

47. 发明授权

US08232832B2 Voltage adder circuit and D/A converter circuit 有权
标题翻译：电压加法器电路和D / A转换电路
公开(公告)号：US08232832B2
公开(公告)日：2012-07-31
申请号：US12928529
申请日：2010-12-14
申请人： Nobuaki Tsuji , Toshio Maejima
发明人： Nobuaki Tsuji , Toshio Maejima
IPC分类号： G06G7/14
CPC分类号： H03F3/45183 , H03F3/45475 , H03F2203/45138 , H03F2203/45674
摘要： A voltage adder circuit includes an amplifier circuit having a first operational amplifier and into which a first voltage is input, a circuit that supplies an output current to the amplifier circuit, and a current providing section that detects the output current of the circuit and supplies an output current equal to the output current of the circuit in magnitude so that the output current of the circuit is prevented from inputting to or outputting from the first operational amplifier through an output terminal of the first operational amplifier. A second voltage is input into the circuit.
摘要翻译：电压加法器电路包括具有第一运算放大器并且输入第一电压的放大器电路，向放大器电路提供输出电流的电路以及检测电路的输出电流并提供电流的电流提供部分输出电流等于电路的输出电流的大小，从而防止电路的输出电流通过第一运算放大器的输出端输入或从第一运算放大器输出。第二电压被输入到电路中。

48. 发明授权

US07924089B2 Offset voltage correction circuit and class D amplifier 有权
公开(公告)号：US07924089B2
公开(公告)日：2011-04-12
申请号：US12807162
申请日：2010-08-30
申请人： Yasuomi Tanaka , Nobuaki Tsuji , Hirotaka Kawai
发明人： Yasuomi Tanaka , Nobuaki Tsuji , Hirotaka Kawai
IPC分类号： H03F3/38
CPC分类号： H03F3/217
摘要： A class D amplifier includes an input unit that inputs an input signal and an integrator which includes a differential operational amplifier having an offset voltage correction function. The integrator integrates the input signal input. A pulse-width modulator modulates the integration result of the integrator to generate a pulse signal having a pulse width reflective of the integration result. An output unit outputs the pulse signal. A feedback unit superimposes a signal output from the output unit on the input signal and feeds back the superimposed signal to the integrator. An input controller selectively set the input unit to a state where no signal is input. An output controller sets a voltage of an output from the feedback unit to a constant voltage.

49. 发明授权

US07920082B2 D/A converter circuit and digital input class-D amplifier 有权
标题翻译： D / A转换器电路和数字输入D类放大器
公开(公告)号：US07920082B2
公开(公告)日：2011-04-05
申请号：US12583792
申请日：2009-08-26
申请人： Hirotaka Kawai , Nobuaki Tsuji , Morito Morishima , Yohei Otani
发明人： Hirotaka Kawai , Nobuaki Tsuji , Morito Morishima , Yohei Otani
IPC分类号： H03M1/20
CPC分类号： H03F3/2173 , H03M1/0639 , H03M1/0673 , H03M1/822 , H03M3/328 , H03M3/50 , H03M3/506 , H03M7/3026
摘要： The present invention provides a D/A converter circuit which enables D/A conversion with a high precision and can prevent occurrence of a limit cycle component in the case where an input signal is low, and can also prevent the effect of dither signal from occurring in an analog signal which is a D/A conversion result.A dither signal generation section 505 outputs a dither signal (DITHER) which is an alternating current signal and a reversal dither signal (DITHER_N) inverted from the dither signal. A DEM decoder 502 processes an input digital signal including a component of the dither signal (DITHER), and outputs a plurality of lines of time-series digital signals having a density of “1” or “0” conforming to the input digital signal to be processed. An analog addition section 503 converts a plurality of lines of time-series digital signals and the reversal dither signal (DITHER_N) into an analog signal respectively and adds them, and outputs an analog signal which is a D/A conversion result.
摘要翻译：本发明提供了一种D / A转换器电路，其能够以高精度实现D / A转换，并且可以防止在输入信号低的情况下出现极限循环分量，并且还可以防止抖动信号的影响在作为D / A转换结果的模拟信号中。抖动信号生成单元505输出作为交流信号的抖动信号（DITHER）和从抖动信号反转的反转抖动信号（DITHER_N）。 DEM解码器502处理包括抖动信号（DITHER）分量的输入数字信号，并输出符合输入数字信号的密度为“1”或“0”的多行时间序列数字信号到被处理。模拟加法部分503将多行时间序列数字信号和反相抖动信号（DITHER_N）分别转换为模拟信号并将其相加，并输出作为D / A转换结果的模拟信号。

50. 发明申请

US20110006843A1 Offset voltage correction circuit and class D amplifier 有权
标题翻译：偏置电压校正电路和D类放大器
公开(公告)号：US20110006843A1
公开(公告)日：2011-01-13
申请号：US12807162
申请日：2010-08-30
申请人： Yasuomi Tanaka , Nobuaki Tsuji , Hirotaka Kawai
发明人： Yasuomi Tanaka , Nobuaki Tsuji , Hirotaka Kawai
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： A class D amplifier includes an input unit that inputs an input signal and an integrator which includes a differential operational amplifier having an offset voltage correction function. The integrator integrates the input signal input. A pulse-width modulator modulates the integration result of the integrator to generate a pulse signal having a pulse width reflective of the integration result. An output unit outputs the pulse signal. A feedback unit superimposes a signal output from the output unit on the input signal and feeds back the superimposed signal to the integrator. An input controller selectively set the input unit to a state where no signal is input. An output controller sets a voltage of an output from the feedback unit to a constant voltage.
摘要翻译： D类放大器包括输入单元，其输入输入信号和积分器，该积分器包括具有偏移电压校正功能的差分运算放大器。积分器集成输入信号输入。脉冲宽度调制器调制积分器的积分结果以产生具有反映积分结果的脉冲宽度的脉冲信号。输出单元输出脉冲信号。反馈单元将从输出单元输出的信号叠加在输入信号上，并将叠加的信号反馈给积分器。输入控制器选择性地将输入单元设置为不输入信号的状态。输出控制器将来自反馈单元的输出的电压设置为恒定电压。

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