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1. 发明授权

US06894320B2 Input protection circuit 有权
标题翻译：输入保护电路
公开(公告)号：US06894320B2
公开(公告)日：2005-05-17
申请号：US10244246
申请日：2002-09-16
申请人： Nobuaki Tsuji , Terumitsu Maeno
发明人： Nobuaki Tsuji , Terumitsu Maeno
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L23/60 , H01L23/62 , H01L27/02 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/72
CPC分类号： H01L27/0262
摘要： An input protection circuit is provided which has a high electrostatic discharge (ESD) breakdown voltage and can input a signal in a wide positive and negative voltage range. In a surface layer of a substrate, a well and a field insulating film are formed. An emitter region is formed in the well to form a lateral bipolar transistor having the well as its base. Another emitter region is formed in the surface layer of the substrate to form another lateral bipolar transistor having the well as its collector. A gate electrode layer is formed on the field insulating film between the well and the other emitter region to form a MOS transistor. The emitter region is connected to an input terminal, the well is connected to the gate electrode layer, and the other emitter region and substrate are connected to a ground potential.
摘要翻译：提供一种具有高静电放电（ESD）击穿电压并可在宽的正和负电压范围内输入信号的输入保护电路。在基板的表面层中，形成阱和场绝缘膜。在阱中形成发射极区，以形成具有阱作为其基极的横向双极晶体管。在衬底的表面层中形成另一个发射极区，以形成具有阱作为其集电极的另一横向双极晶体管。在阱和另一个发射极区之间的场绝缘膜上形成栅极电极层，以形成MOS晶体管。发射极区域连接到输入端子，阱连接到栅极电极层，另一个发射极区域和衬底连接到地电位。

2. 发明授权

US07075123B2 Semiconductor input protection circuit 失效
标题翻译：半导体输入保护电路
公开(公告)号：US07075123B2
公开(公告)日：2006-07-11
申请号：US10968685
申请日：2004-10-19
申请人： Nobuaki Tsuji , Masao Noro , Terumitsu Maeno , Seiji Hirade
发明人： Nobuaki Tsuji , Masao Noro , Terumitsu Maeno , Seiji Hirade
IPC分类号： H01L29/74 , H01L23/62
CPC分类号： H01L27/0255 , H01L27/0259 , H01L27/0288
摘要： A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of −2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.
摘要翻译：横向PNP晶体管PB和横向NPN晶体管NB串联连接在输入端子和参考电位（地电位）之间。在晶体管PB中，形成二极管D 1 1。在晶体管NB中，形成二极管D 3 3。当输入+2000V的ESD时，晶体管NB导通，而当输入-2000V的ESD时，晶体管PB导通。能够输入的正信号的电平受到二极管D 3 3的反向击穿电压（例如，18至50V）的限制，而能够输入的负信号的电平为受二极管D 1 1的反向击穿电压（例如，13至15V）的限制。

3. 发明申请

US20050051847A1 Semiconductor input protection circuit 失效
公开(公告)号：US20050051847A1
公开(公告)日：2005-03-10
申请号：US10968685
申请日：2004-10-19
申请人： Nobuaki Tsuji , Masao Noro , Terumitsu Maeno , Seiji Hirade
发明人： Nobuaki Tsuji , Masao Noro , Terumitsu Maeno , Seiji Hirade
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/06 , H01L27/092 , H01L29/74
CPC分类号： H01L27/0255 , H01L27/0259 , H01L27/0288
摘要： A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of −2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.

4. 发明授权

US06847059B2 Semiconductor input protection circuit 有权
标题翻译：半导体输入保护电路
公开(公告)号：US06847059B2
公开(公告)日：2005-01-25
申请号：US09982335
申请日：2001-10-18
申请人： Nobuaki Tsuji , Masao Noro , Terumitsu Maeno , Seiji Hirade
发明人： Nobuaki Tsuji , Masao Noro , Terumitsu Maeno , Seiji Hirade
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/06 , H01L27/092 , H01L29/74 , H01L23/62
CPC分类号： H01L27/0255 , H01L27/0259 , H01L27/0288
摘要： A lateral PNP transistor PB and a lateral NPN transistor NB are serially connected between an input terminal and a reference potential (ground potential). In the transistor PB, a diode D1 is formed. In the transistor NB, a diode D3 is formed. When an ESD of +2000 V is input, the transistor NB turns on, whereas when an ESD of −2000 V is input, the transistor PB turns on. The level of a positive signal capable of being input is limited by the inverse breakdown voltage (e.g., 18 to 50 V) of the diode D3, whereas the level of a negative signal capable of being input is limited by the inverse breakdown voltage (e.g., 13 to 15 V) of the diode D1.
摘要翻译：横向PNP晶体管PB和横向NPN晶体管NB串联连接在输入端子和参考电位（地电位）之间。在晶体管PB中形成二极管D1。在晶体管NB中，形成二极管D3。当输入+2000V的ESD时，晶体管NB导通，而当输入-2000V的ESD时，晶体管PB导通。能够输入的正信号的电平受到二极管D3的反向击穿电压（例如，18至50V）的限制，而能够被输入的负信号的电平受到反向击穿电压的限制（例如，，13〜15V）。

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