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41. 发明授权

US06809395B1 Isolation structure having trench structures formed on both side of a locos 失效
标题翻译：具有形成在位置的两侧的沟槽结构的隔离结构
公开(公告)号：US06809395B1
公开(公告)日：2004-10-26
申请号：US09369579
申请日：1999-08-06
申请人： Fernando Gonzales , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
发明人： Fernando Gonzales , Mike Violette , Nanseng Jeng , Aftab Ahmad , Klaus Schuegraf
IPC分类号： H01L2900
CPC分类号： H01L21/76202 , H01L21/76221 , Y10S148/05
摘要： A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate. The regrown oxide layer will encroach into all exposed surfaces of active areas and will grow also in the microtrench. Alternatively, the pad oxide layer is etched substantially uniformly at regions distant from nitride layer, whereas the etchant concentrates the etch against the nitride layer such that etching is accelerated at this location. Because of accelerated etching at this location, a breach in the pad oxide layer forms before etching of the pad oxide layer has been generally penetrated. The breach has a width of sub-photolithographic limits preparatory to formation of a microtrench thereunder.
摘要翻译：通过硅的局部氧化来扩大半导体结构衬垫氧化物层以形成场氧化物。回蚀使场氧化物的最薄部分后退，使得半导体衬底的一部分露出。通过半导体衬底的暴露部分的蚀刻在场氧化物和氮化物层之间形成微切口，其横向尺寸小于通过常规光刻法目前可实现的横向尺寸。然后通过氧化物或氮化物生长或通过沉积电介质材料来填充微切口。在另一个实施例中，微沟槽的形成如上所述进行，但是在形成沟槽之后立即去除氮化物层。或者，剥除焊盘氧化物层，并重新生长新的氧化物层，其基本上覆盖半导体衬底的有源区域的所有暴露表面。再生的氧化物层将侵蚀到活性区域的所有暴露表面，并且还将在微型扳手中生长。或者，在远离氮化物层的区域处基本上均匀地蚀刻焊盘氧化物层，而蚀刻剂将蚀刻集中到氮化物层上，使得在该位置加速蚀刻。由于在该位置处的加速蚀刻，在氧化垫层的蚀刻之前形成的衬垫氧化物层中的破裂已经被普遍渗透。该破裂具有准备在其下形成微型切割器的副光刻极限的宽度。

42. 发明授权

US06444529B1 Methods of forming integrated circuitry and methods of forming elevated source/drain regions of a field effect transistor 有权
公开(公告)号：US06444529B1
公开(公告)日：2002-09-03
申请号：US09771449
申请日：2001-01-26
申请人： Aftab Ahmad , Lyle Jones
发明人： Aftab Ahmad , Lyle Jones
IPC分类号： H01L21336
摘要： Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprising undoped semiconductive material is formed laterally proximate the transistor gate line and joins with semiconductive material of the substrate and comprises elevated source/drain material for a transistor of the line. Subsequently, conductivity-modifying impurity is provided into the elevated source/drain material. In another embodiment, a common step is utilized to provide conductivity enhancing impurity into both elevated source/drain material and material of the gate line. In another embodiment, the undoped semiconductive layer is first patterned and etched to provide elevated source/drain regions prior to provision of the conductivity-modifying impurity. In another embodiment, the semiconductive material is first patterned with conductivity modifying impurity being provided into selected portions of the semiconductive material. Undoped semiconductive portions are subsequently removed selectively relative to doped semiconductive material portions.

43. 发明授权

US06333539B1 Semiconductor transistor devices and methods for forming semiconductor transistor devices 失效
标题翻译：半导体晶体管器件和用于形成半导体晶体管器件的方法
公开(公告)号：US06333539B1
公开(公告)日：2001-12-25
申请号：US09167174
申请日：1998-10-06
申请人： Aftab Ahmad , David J. Keller
发明人： Aftab Ahmad , David J. Keller
IPC分类号： H01L2976
CPC分类号： H01L29/6653 , H01L21/823814 , H01L21/823864 , H01L29/6659 , H01L29/7833
摘要： In one aspect, the invention encompasses a transistor device comprising a region of a semiconductor material wafer, and a transistor gate over a portion of the region. The transistor gate has a pair of opposing sidewalls which are a first sidewall and a second sidewall. The device further comprises a pair of opposing sidewall spacers adjacent the sidewalls of the transistor gate and a pair of opposing first conductivity type source/drain regions within the semiconductor material wafer proximate the transistor gate. One of the sidewall spacers extends along the first sidewall of the gate and the other of the sidewall spacers extends along the second sidewall of the gate. The entirety of the semiconductor wafer material under one of the sidewall spacers being defined as a first segment of the semiconductor wafer material, and the entirety of the semiconductor wafer material which is under the other of the sidewall spacers being defined as a second segment of the semiconductor wafer material. The first and second segments of the semiconductor material wafer are separated from the first and second source/drain regions by first and second gap regions, respectively, of the semiconductor material wafer. The device further comprises a pair of opposing second conductivity type halo regions within the first and second gap regions.
摘要翻译：在一个方面，本发明包括一种晶体管器件，其包括半导体材料晶片的区域和该区域的一部分上的晶体管栅极。晶体管栅极具有一对相对的侧壁，它们是第一侧壁和第二侧壁。该器件还包括邻近晶体管栅极的侧壁的一对相对的侧壁间隔物和靠近晶体管栅极的半导体材料晶片内的一对相对的第一导电类型源极/漏极区域。侧壁间隔件中的一个沿着栅极的第一侧壁延伸，并且另一个侧壁间隔件沿着栅极的第二侧壁延伸。将侧壁间隔物之一的半导体晶片材料的整体定义为半导体晶片材料的第一段，并且位于另一侧壁间隔物之下的整个半导体晶片材料被定义为第二段半导体晶片材料。半导体材料晶片的第一和第二段分别由半导体材料晶片的第一和第二间隙区域与第一和第二源极/漏极区分离。该装置还包括在第一和第二间隙区域内的一对相对的第二导电类型的晕圈区域。

44. 发明授权

US6150204A Semiconductor processing method of fabricating field effect transistors 有权
标题翻译：制造场效应晶体管的半导体处理方法
公开(公告)号：US6150204A
公开(公告)日：2000-11-21
申请号：US192958
申请日：1998-11-16
申请人： Aftab Ahmad , Kirk Prall
发明人： Aftab Ahmad , Kirk Prall
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/6653 , H01L21/823814
摘要： In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second transistor gate. In another aspect, a semiconductor processing method includes: a) providing a semiconductor substrate; b) providing a transistor gate over the semiconductor substrate; c) providing spacers adjacent the transistor gate; d) providing electrically conductive source and drain implant regions within the substrate operatively adjacent the transistor gate; e) implanting a conductivity enhancing dopant into the previously formed electrically conductive source and drain regions; and f) driving the conductivity enhancing dopant under the spacers to form graded junction regions.
摘要翻译：在本发明的一个方面，半导体处理方法包括：a）提供半导体衬底; b）限定半导体衬底的第一导电类型区域和第二导电类型区域; c）在所述第一类型区域上提供限定与其可操作地相邻的第一源区域和第一漏极区域的第一晶体管栅极; d）在所述第二类型区域上提供限定与其可操作地相邻的第二源极区域和第二漏极区域的第二晶体管栅极; 以及e）通过所述第一导电区域的所述第一源极和漏极区域以及所述第二导电区域的所述第二源极和漏极区域覆盖所述第二导电类型的电导率增强掺杂剂，以在所述衬底内提供第二导电类型的常规LDD注入区域可操作地与第一晶体管栅极相邻并且在衬底内提供可操作地邻近第二晶体管栅极的第二导电类型的晕圈注入区域。另一方面，半导体处理方法包括：a）提供半导体衬底; b）在半导体衬底上提供晶体管栅极; c）提供与晶体管栅极相邻的间隔物; d）在所述衬底内提供与所述晶体管栅极可操作地相邻的导电源极和漏极注入区域; e）将电导率增强掺杂剂注入到先前形成的导电源极和漏极区域中; 以及f）在所述间隔物下驱动所述导电性增强掺杂剂以形成渐变连接区域。

45. 发明授权

US06130137A Method of forming a resistor and integrated circuitry having a resistor construction 有权
标题翻译：形成电阻器的方法和具有电阻器结构的集成电路
公开(公告)号：US06130137A
公开(公告)日：2000-10-10
申请号：US170792
申请日：1998-10-13
申请人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
发明人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/20
摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.
摘要翻译：从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。

46. 发明授权

US5939761A Method of forming a field effect transistor 失效
标题翻译：形成场效应晶体管的方法
公开(公告)号：US5939761A
公开(公告)日：1999-08-17
申请号：US929693
申请日：1997-09-15
申请人： Charles H. Dennison , Aftab Ahmad
发明人： Charles H. Dennison , Aftab Ahmad
IPC分类号： H01L21/336 , H01L21/60 , H01L21/762 , H01L29/76
CPC分类号： H01L21/76897 , H01L21/76221 , H01L29/6656 , H01L29/66575 , Y10S438/975
摘要： A method for forming a field effect transistor on a substrate includes providing a wordline on the substrate; providing composite masking spacers laterally outward relative to the wordline, the composite masking spacers comprising at least two different materials; removing at least one of the materials of the composite masking spacers to effectively expose the substrate area adjacent to the wordline for conductivity enhancing doping; and subjecting the effectively exposed substrate to conductivity enhancing doping to form source/drain regions. Another aspect of the invention is to provide a method for forming a field effect transistor including providing a gate on the substrate, providing a first layer of nitride over the gate; providing a second layer of a masking material over the first layer of nitride; anisotropically etching the first and second layers to define composite oxidation masking spacers positioned laterally outward relative to the patterned gate; and exposing the substrate to oxidation condition effective to form a field oxide region laterally outward of the composite oxidation masking spacers, the composite oxidation masking spacers effectively restricting oxidation of the substrate therebeneath.
摘要翻译：在衬底上形成场效应晶体管的方法包括在衬底上提供字线; 提供相对于所述字线横向向外的复合掩模间隔物，所述复合掩模间隔物包括至少两种不同的材料; 去除所述复合掩模间隔物的至少一种材料以有效地暴露与所述字线相邻的衬底区域以进行导电性增强掺杂; 以及对有效暴露的衬底进行电导率增强掺杂以形成源极/漏极区域。本发明的另一方面是提供一种用于形成场效应晶体管的方法，包括在衬底上提供栅极，在栅极上提供第一层氮化物; 在所述第一氮化物层上提供掩蔽材料的第二层; 各向异性地蚀刻第一层和第二层以限定相对于图案化的浇口横向向外定位的复合氧化掩模间隔物; 以及将所述衬底暴露于有效地形成所述复合氧化掩模间隔物的横向外部的场氧化物区域的氧化条件，所述复合氧化掩蔽间隔物有效地限制了其下的衬底的氧化。

47. 发明授权

US5923078A Method of forming a resistor and integrated circuitry having a resistor construction 失效
公开(公告)号：US5923078A
公开(公告)日：1999-07-13
申请号：US079368
申请日：1998-05-15
申请人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
发明人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
IPC分类号： H01L21/329 , H01L27/06 , H01L27/08 , H01L29/00
CPC分类号： H01L29/66166 , H01L27/0629 , H01L27/0802
摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

48. 发明授权

US5821150A Method of forming a resistor and integrated circuitry having a resistor construction 失效
公开(公告)号：US5821150A
公开(公告)日：1998-10-13
申请号：US954970
申请日：1997-10-20
申请人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
发明人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
IPC分类号： H01L21/02 , H01L27/06 , H01L27/08 , H01L21/8234
CPC分类号： H01L28/20 , H01L27/0629 , H01L27/0802 , Y10S148/136
摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

49. 发明授权

US5780920A Method of forming a resistor and integrated circuitry having a resistor construction 失效
公开(公告)号：US5780920A
公开(公告)日：1998-07-14
申请号：US680332
申请日：1996-07-11
申请人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
发明人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
IPC分类号： H01L21/02 , H01L27/06 , H01L27/08 , H01L29/00
CPC分类号： H01L28/20 , H01L27/0629 , H01L27/0802 , Y10S148/136
摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

50. 发明授权

US5702976A Shallow trench isolation using low dielectric constant insulator 失效
标题翻译：使用低介电常数绝缘子的浅沟槽隔离
公开(公告)号：US5702976A
公开(公告)日：1997-12-30
申请号：US547620
申请日：1995-10-24
申请人： Klaus F. Schuegraf , Aftab Ahmad
发明人： Klaus F. Schuegraf , Aftab Ahmad
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced wench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.
摘要翻译：公开了一种浅沟槽隔离，其中沟槽深度减小到超过现有技术工艺中所达到的深度。减小的深度深度有助于消除在沟槽再填充过程期间形成空隙，并且在最终隔离结构中提供更大的平坦度。通过利用具有低介电常数的再填充介电材料，通过减小沟槽深度实现有效的器件隔离。

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