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    • 42. 发明申请
    • Semiconductor memory device and core layout thereof
    • 半导体存储器件及其核心布局
    • US20060215480A1
    • 2006-09-28
    • US11316878
    • 2005-12-27
    • Hye-jin KimChoong-keun KwakWoo-yeong ChoSang-beom Kang
    • Hye-jin KimChoong-keun KwakWoo-yeong ChoSang-beom Kang
    • G11C8/00
    • G11C13/0028G11C13/0004
    • A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are natural numbers. The memory device further includes a plurality of word line driving circuits which respectively control a voltage of the sub word lines according to a logic level of each corresponding global word line and inputted address signals, and a plurality of control circuits which transmit the address signals to the word line driving circuits or interrupt transmission of the address signals according to the logic level of the global word line. Each of the word line driving circuits includes a first transistor which maintains the voltage of the respective sub word line at a first voltage and a second transistor which maintains the voltage of the sub word line at the first voltage or a second voltage.
    • 一个方面的半导体存储器件包括包括n个全局字线的存储单元块,以及n个全局字线中的每一个的对应m个子字线,其中n和m是自然数。 存储装置还包括多个字线驱动电路,其分别根据每个对应的全局字线和输入的地址信号的逻辑电平分别控制子字线的电压,以及多个控制电路,其将地址信号发送到 字线驱动电路或根据全局字线的逻辑电平中断地址信号的传输。 每个字线驱动电路包括将相应子字线的电压维持在第一电压的第一晶体管和将子字线的电压维持在第一电压或第二电压的第二晶体管。