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41. 发明申请

US20070014150A1 Phase change random access memory (PRAM) device having variable drive voltages 有权
标题翻译：具有可变驱动电压的相变随机存取存储器（PRAM）装置
公开(公告)号：US20070014150A1
公开(公告)日：2007-01-18
申请号：US11319601
申请日：2005-12-29
申请人： Woo-yeong Cho , Du-eung Kim , Sang-beom Kang , Choong-keun Kwak
发明人： Woo-yeong Cho , Du-eung Kim , Sang-beom Kang , Choong-keun Kwak
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C13/0038 , G11C5/145 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/009
摘要： A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.
摘要翻译：一个方面的相变存储器件包括包括多个相变存储单元，写升压电路和写驱动器的存储器阵列。写升压电路升压第一电压并响应于第一操作模式中的控制信号输出第一控制电压，并且在第二操作模式中响应于控制信号升高第一电压并输出第二控制电压，并且第三操作模式。写入驱动器由第一操作模式中的第一控制电压驱动，并将数据写入存储器阵列的所选存储单元。

42. 发明申请

US20060215480A1 Semiconductor memory device and core layout thereof 失效
标题翻译：半导体存储器件及其核心布局
公开(公告)号：US20060215480A1
公开(公告)日：2006-09-28
申请号：US11316878
申请日：2005-12-27
申请人： Hye-jin Kim , Choong-keun Kwak , Woo-yeong Cho , Sang-beom Kang
发明人： Hye-jin Kim , Choong-keun Kwak , Woo-yeong Cho , Sang-beom Kang
IPC分类号： G11C8/00
CPC分类号： G11C13/0028 , G11C13/0004
摘要： A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are natural numbers. The memory device further includes a plurality of word line driving circuits which respectively control a voltage of the sub word lines according to a logic level of each corresponding global word line and inputted address signals, and a plurality of control circuits which transmit the address signals to the word line driving circuits or interrupt transmission of the address signals according to the logic level of the global word line. Each of the word line driving circuits includes a first transistor which maintains the voltage of the respective sub word line at a first voltage and a second transistor which maintains the voltage of the sub word line at the first voltage or a second voltage.
摘要翻译：一个方面的半导体存储器件包括包括n个全局字线的存储单元块，以及n个全局字线中的每一个的对应m个子字线，其中n和m是自然数。存储装置还包括多个字线驱动电路，其分别根据每个对应的全局字线和输入的地址信号的逻辑电平分别控制子字线的电压，以及多个控制电路，其将地址信号发送到字线驱动电路或根据全局字线的逻辑电平中断地址信号的传输。每个字线驱动电路包括将相应子字线的电压维持在第一电压的第一晶体管和将子字线的电压维持在第一电压或第二电压的第二晶体管。

43. 发明申请

US20060013058A1 Phase change memory device for use in a burst read operation and a data reading method thereof 有权
标题翻译：用于突发读取操作的相变存储器件及其数据读取方法
公开(公告)号：US20060013058A1
公开(公告)日：2006-01-19
申请号：US11184184
申请日：2005-07-19
申请人： Sang-Beom Kang , Woo-Yeong Cho
发明人： Sang-Beom Kang , Woo-Yeong Cho
IPC分类号： G11C8/00
CPC分类号： G11C13/0004 , G11C7/1027 , G11C13/004 , G11C2013/0054
摘要： A phase change memory device for use in a burst read operation and a data reading method are provided. The memory device includes a plurality of bit lines and a plurality of word lines. A memory cell array block has a plurality of phase change memory cells that are connected to cross points of the plurality of bit lines and the plurality of word lines. A sense amplifier block is connected to corresponding bit lines, and latches data of memory cells connected to the same word line simultaneously during a burst read operation, and then provides the latched data in response to a column address.
摘要翻译：提供了一种用于突发读取操作和数据读取方法的相变存储器件。存储器件包括多个位线和多个字线。存储单元阵列块具有连接到多个位线和多个字线的交叉点的多个相变存储单元。读出放大器块连接到对应的位线，并且在突发读取操作期间同时锁存连接到相同字线的存储器单元的数据，然后响应于列地址提供锁存的数据。

44. 发明授权

US09042152B2 Data read circuit, a non-volatile memory device having the same, and a method of reading data from the non-volatile memory device 有权
标题翻译：数据读取电路，具有该数据读出电路的非易失性存储器件以及从非易失性存储器件读取数据的方法
公开(公告)号：US09042152B2
公开(公告)日：2015-05-26
申请号：US13562871
申请日：2012-07-31
申请人： Chan-kyung Kim , Hong-sun Hwang , Chul-woo Park , Sang-beom Kang , Hyung-rok Oh
发明人： Chan-kyung Kim , Hong-sun Hwang , Chul-woo Park , Sang-beom Kang , Hyung-rok Oh
IPC分类号： G11C11/00 , G11C13/00 , G11C11/16 , G11C7/06 , G11C7/08 , G11C7/14 , G11C11/56
CPC分类号： G11C13/0033 , G11C7/062 , G11C7/067 , G11C7/08 , G11C7/14 , G11C11/1673 , G11C11/1693 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C2013/0042 , G11C2013/0054
摘要： A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.
摘要翻译：包括具有多个存储单元的单元阵列和读出放大电路的非易失性存储器件。感测放大电路被配置为在存储单元的数据读取操作期间接收存储单元的数据电压，第一参考电压和第二参考电压，基于数据电压和数据电压之间的电压电平差产生差分输出信号第一和第二参考电压，并将差分输出信号作为从存储单元读取的数据输出。

45. 发明授权

US08780617B2 Semiconductor memory device and method of performing burn-in test on the same 有权
标题翻译：半导体存储器件及其在其上执行老化测试的方法
公开(公告)号：US08780617B2
公开(公告)日：2014-07-15
申请号：US13653782
申请日：2012-10-17
申请人： Sang-beom Kang , Joon-hyung Lee
发明人： Sang-beom Kang , Joon-hyung Lee
IPC分类号： G11C11/16 , G11C11/02 , G11C7/00 , G11C7/12 , G11C8/08 , G11C8/10 , G11C29/08 , G11C16/10 , G11C29/34 , G11C8/12
CPC分类号： G11C29/08 , G11C5/06 , G11C8/08 , G11C8/10 , G11C8/12 , G11C11/16 , G11C11/1659 , G11C11/1675 , G11C11/1697 , G11C13/00 , G11C16/10 , G11C29/12005 , G11C29/18 , G11C29/34 , G11C2029/1802
摘要： A semiconductor memory device includes a cell array having a plurality of memory cells, each memory cell including a resistive element and a cell transistor between a bit line and a source line, and a source line voltage supply unit configured to supply, in a normal mode, a reference source line voltage to the source line, and in a test mode, a first source line voltage to the source line when data in a first state is recorded and a second source line voltage to the source line when data in a second state is recorded, the first source line voltage being lower than the reference source line voltage, and the second source line voltage being higher than the reference source line voltage.
摘要翻译：半导体存储器件包括具有多个存储单元的单元阵列，每个存储单元包括位线和源极线之间的电阻元件和单元晶体管，以及源极线电压供给单元，被配置为以正常模式，到源极线的参考源极线电压，并且在测试模式中，当记录处于第一状态的数据时，到源极线的第一源极线电压，以及当处于第二状态的数据时到源极线的第二源极线电压，第一源极线电压低于基准源极线电压，第二源极线电压高于基准源极线电压。

46. 发明授权

US08611121B2 Stacked memory devices 有权
标题翻译：堆叠式存储器件
公开(公告)号：US08611121B2
公开(公告)日：2013-12-17
申请号：US12662785
申请日：2010-05-04
申请人： Seung-eon Ahn , Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Hyun-ho Choi
发明人： Seung-eon Ahn , Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Hyun-ho Choi
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/02 , G11C8/10 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/71 , G11C2213/72
摘要： A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups.
摘要翻译：层叠的存储器件可以包括衬底，顺序地堆叠在衬底上的多个存储器组，每个存储器组包括至少一个存储器层，多个X译码器层，所述多个X译码器层中的至少一个是设置在所述多个存储器组中的每个相邻的两个存储器组之间，以及与所述多个X解码器层交替布置的多个Y译码器层，所述多个Y译码器层中的至少一个设置在每个相邻的两个存储器组之间的多个存储器组。

47. 发明申请

US20130311717A1 MAGNETIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：磁性随机存取存储器
公开(公告)号：US20130311717A1
公开(公告)日：2013-11-21
申请号：US13768858
申请日：2013-02-15
申请人： Chan-kyung Kim , Dong-seok Kang , Hye-jin Kim , Chul-woo Park , Dong-hyun Sohn , Yun-sang Lee , Sang-beom Kang , Hyung-rok Oh , Soo-ho Cha
发明人： Chan-kyung Kim , Dong-seok Kang , Hye-jin Kim , Chul-woo Park , Dong-hyun Sohn , Yun-sang Lee , Sang-beom Kang , Hyung-rok Oh , Soo-ho Cha
IPC分类号： G11C11/16 , G06F12/02
CPC分类号： G11C11/165 , G06F12/0246 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.
摘要翻译：公开了一种磁性随机存取存储器（MRAM）及其存储器模块，包括该存储器模块的存储器系统及其控制方法。 MRAM包括被配置为根据磁化方向在至少两个状态之间改变的磁存储单元和支持多个操作模式的模式寄存器。

48. 发明申请

US20130064008A1 DATA READ CIRCUIT, NONVOLATILE MEMORY DEVICE COMPRISING DATA READ CIRCUIT, AND METHOD OF READING DATA FROM NONVOLATILE MEMORY DEVICE 有权
标题翻译：数据读取电路，包含数据读取电路的非易失性存储器件以及从非易失性存储器件读取数据的方法
公开(公告)号：US20130064008A1
公开(公告)日：2013-03-14
申请号：US13604688
申请日：2012-09-06
申请人： CHAN-KYUNG KIM , HONG-SUN HWANG , CHUL-WOO PARK , SANG-BEOM KANG , HYUNG-ROK OH
发明人： CHAN-KYUNG KIM , HONG-SUN HWANG , CHUL-WOO PARK , SANG-BEOM KANG , HYUNG-ROK OH
IPC分类号： G11C7/10 , G11C11/02
CPC分类号： G11C5/145 , G11C7/12 , G11C11/1673
摘要： A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.
摘要翻译：非易失性存储器件包括非易失性单元阵列，其包括存储单元和参考单元，钳位电路电连接到存储单元并且被配置为在读取操作期间钳位施加到数据感测线的电压，以及钳位电压产生单元被配置为响应于具有基于参考单元的电平的第一电压产生钳位电压，并且将钳位电压反馈到钳位电路。

49. 发明授权

US08238148B2 Semiconductor device having architecture for reducing area and semiconductor system including the same 有权
标题翻译：具有用于减小面积的结构的半导体器件和包括其的半导体系统
公开(公告)号：US08238148B2
公开(公告)日：2012-08-07
申请号：US12652190
申请日：2010-01-05
申请人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Jung Min Lee , Hyun Ho Choi
发明人： Ho Jung Kim , Chul Woo Park , Sang Beom Kang , Jung Min Lee , Hyun Ho Choi
IPC分类号： G11C11/00 , G11C7/10 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1039 , G11C7/1033 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C13/0004 , G11C2207/107
摘要： A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially output from the plurality of registers to the memory cell array during a write operation. The semiconductor device also includes a sense amplifier circuit configured to sense and amplify pre-fetch unit data sequentially output from the memory cell array and to sequentially store the amplified pre-fetch unit data in the plurality of registers, respectively, during a read operation.
摘要翻译：提供了具有用于减小面积的架构的半导体器件。半导体器件包括存储单元阵列，该存储单元阵列包括多个非易失性存储器单元，多个寄存器，每个寄存器被配置为存储预取单元数据;以及写入驱动器电路，被配置为写入从多个单元顺序地输出的预取单元数据的寄存器在写操作期间到存储单元阵列。半导体器件还包括读出放大器电路，其被配置为感测并放大从存储单元阵列顺序输出的预取单元数据，并且在读取操作期间分别顺序地将放大的预取单元数据存储在多个寄存器中。

50. 发明授权

US08144535B2 Test circuit for measuring resistance distribution of memory cells and semiconductor system including the same 有权
标题翻译：用于测量存储器单元和包括其的半导体系统的电阻分布的测试电路
公开(公告)号：US08144535B2
公开(公告)日：2012-03-27
申请号：US12588192
申请日：2009-10-07
申请人： Sang Beom Kang , Ho Jung Kim
发明人： Sang Beom Kang , Ho Jung Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/16 , G11C29/50008
摘要： The test circuit for measuring a resistance distribution of memory cells includes a sensing circuit and a digital value generation circuit. The sensing circuit compares a reference voltage with a voltage of a sensing node receiving a voltage of a bit line connected with a resistive element and generates a sensing signal. The digital value generation circuit generates a digital value corresponding to a resistance-capacitance (RC) delay of the bit line in response to the sensing signal from the sensing circuit.
摘要翻译：用于测量存储单元的电阻分布的测试电路包括感测电路和数字值产生电路。感测电路将参考电压与接收与电阻元件连接的位线的电压的感测节点的电压进行比较，并产生感测信号。响应于来自感测电路的感测信号，数字值产生电路产生对应于位线的电阻 - 电容（RC）延迟的数字值。

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