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41. 发明授权

US6080640A Metal attachment method and structure for attaching substrates at low temperatures 失效
标题翻译：用于在低温下安装基板的金属附着方法和结构
公开(公告)号：US6080640A
公开(公告)日：2000-06-27
申请号：US45324
申请日：1998-03-20
申请人： Mark I. Gardner , Fred Hause , Daniel Kadosh
发明人： Mark I. Gardner , Fred Hause , Daniel Kadosh
IPC分类号： H01L21/768 , H01L21/98 , H01L23/532 , H01L25/065 , H01L21/30 , H01L21/46
CPC分类号： H01L25/50 , H01L21/76801 , H01L21/76834 , H01L23/5329 , H01L24/80 , H01L25/0657 , H01L2224/05571 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2225/06513 , H01L2225/06541 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/3011
摘要： A high density integrated circuit structure and method of making the same includes providing a first silicon substrate structure having semiconductor device formations in accordance with a first circuit implementation and metal interlevel lines disposed on a top surface thereof and a second silicon substrate structure having a second circuit implementation and metal interlevel lines disposed on a top surface thereof. The first substrate structure includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from is the low-K dielectric, the metal interlevel lines of the first silicon substrate structure have a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. The second substrate structure also includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines having a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. Lastly, the first substrate structure is low temperature bonded to the second substrate structure at respective metal interlevel lines of the first and second substrate structures.
摘要翻译：高密度集成电路结构及其制造方法包括提供具有根据第一电路实现的半导体器件结构的第一硅衬底结构和设置在其顶表面上的金属层间线以及具有第二电路的第二硅衬底结构实施和设置在其顶表面上的金属层间线。第一衬底结构包括布置在金属层间线之间的平坦化低K电介质和将金属层间线与低K电介质隔开的保护涂层，第一硅衬底结构的金属层间线具有在介电K值在2.0-3.8范围内的低K电介质。第二基板结构还包括布置在金属层间线之间的平坦化的低K电介质和将金属层间线与低K电介质隔开的保护涂层，金属层间线具有小于500°的熔融温度并且介电K值在2.0-3.8范围内的低K电介质。最后，第一衬底结构在第一和第二衬底结构的相应的金属层间线处被低温地结合到第二衬底结构。

42. 发明授权

US6074919A Method of forming an ultrathin gate dielectric 有权
标题翻译：形成超薄栅极电介质的方法
公开(公告)号：US6074919A
公开(公告)日：2000-06-13
申请号：US234561
申请日：1999-01-20
申请人： Mark I. Gardner , Thien T. Nguyen
发明人： Mark I. Gardner , Thien T. Nguyen
IPC分类号： H01L21/28 , H01L21/336 , H01L27/06 , H01L29/417 , H01L29/49 , H01L29/51
CPC分类号： H01L29/513 , H01L21/28052 , H01L21/28194 , H01L27/0688 , H01L29/41775 , H01L29/41783 , H01L29/66583 , H01L21/28202 , H01L29/495 , H01L29/517 , H01L29/518
摘要： A method is provided for fabricating a transistor, the method including forming a semiconducting layer above a substrate layer, forming a first dielectric layer above the semiconducting layer and forming a sacrificial layer above the first dielectric layer. The method also includes forming an opening in the sacrificial layer, the first dielectric layer and the semiconducting layer to expose a channel region in the substrate layer. The method further includes forming a gate dielectric above the channel region in the substrate layer within the opening and forming a gate conductor above the gate dielectric within the opening. Moreover, the method includes removing the sacrificial layer to expose sides of the gate conductor and introducing a dopant into the semiconducting layer to form doped source/drain regions. In addition, the method includes forming dielectric spacers adjacent the gate conductor.
摘要翻译：提供了一种用于制造晶体管的方法，所述方法包括在衬底层上形成半导体层，在半导体层上形成第一介电层，并在第一介电层上方形成牺牲层。该方法还包括在牺牲层，第一介电层和半导体层中形成开口以暴露衬底层中的沟道区。该方法还包括在开口内的衬底层中的沟道区域的上方形成栅极电介质，并在开口内部的栅极电介质的上方形成栅极导体。此外，该方法包括去除牺牲层以暴露栅极导体的侧面并将掺杂剂引入到半导体层中以形成掺杂的源极/漏极区域。此外，该方法包括在栅极导体附近形成介电间隔物。

43. 发明授权

US6074904A Method and structure for isolating semiconductor devices after transistor formation 失效
标题翻译：在晶体管形成之后隔离半导体器件的方法和结构
公开(公告)号：US6074904A
公开(公告)日：2000-06-13
申请号：US63796
申请日：1998-04-21
申请人： Thomas E. Spikes, Jr. , Mark W. Michael , Mark I. Gardner , Robert Dawson
发明人： Thomas E. Spikes, Jr. , Mark W. Michael , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/762 , H01L21/8238
CPC分类号： H01L21/823878 , H01L21/76237
摘要： A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes a first pair of source/drain regions on either side of a first channel region and a second pair of source/drain regions on either side of a second channel region. One of the first pair of source/drain regions is proximal to one of the second pair of source/drain regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. An isolation trench is formed through the proximal source/drain regions and the trench is filled with a trench dielectric material such that the proximal source/drain regions are electrically isolated whereby the first transistor is electrically isolated from the second transistor.
摘要翻译：一种用于隔离半导体器件的方法，包括提供半导体衬底。半导体衬底包括在第一沟道区的任一侧上的第一对源/漏区和在第二沟道区的任一侧上的第二对源极/漏极区。第一对源极/漏极区域中的一个靠近第二对源极/漏极区域中的一个。第一和第二横向位移的MOS晶体管部分地形成在半导体衬底内。通过近端源极/漏极区域形成隔离沟槽，并且沟槽填充有沟槽电介质材料，使得近端源极/漏极区域被电隔离，由此第一晶体管与第二晶体管电隔离。

44. 发明授权

US6069398A Thin film resistor and fabrication method thereof 失效
标题翻译：薄膜电阻及其制造方法
公开(公告)号：US6069398A
公开(公告)日：2000-05-30
申请号：US905306
申请日：1997-08-01
申请人： Daniel Kadosh , Mark I. Gardner , Frederick N. Hause
发明人： Daniel Kadosh , Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/02 , H01L27/06 , H01L29/00
CPC分类号： H01L28/20 , H01L27/0688
摘要： A resistor is formed between devices in an integrated circuit by forming a patterned trench in an intralayer dielectric (ILD) deposited over the devices, filling the trench with polysilicon and planarizing the polysilicon. The resistance of the resistor is defined by determining and selecting the size and form of the trench including the width, length, depth and orientation of the trench. In some embodiments, the resistance of the resistor is also controlled by adding selected amounts and species of dopants to the polysilicon. In some embodiments, the resistance is controlled by directly saliciding the polysilicon in the trench.
摘要翻译：通过在沉积在器件上的层间电介质（ILD）中形成图案化沟槽，用多晶硅填充沟槽并平坦化多晶硅，在集成电路中的器件之间形成电阻器。通过确定和选择包括沟槽的宽度，长度，深度和取向的沟槽的尺寸和形式来限定电阻器的电阻。在一些实施例中，电阻器的电阻也通过将选定量和种类的掺杂剂添加到多晶硅来控制。在一些实施例中，通过在沟槽中直接浇注多晶硅来控制电阻。

45. 发明授权

US6060369A Nitrogen bearing sacrificial oxide with subsequent high nitrogen dopant profile for high performance MOSFET 失效
标题翻译：含氮牺牲氧化物，具有高性能MOSFET的高氮掺杂剂分布
公开(公告)号：US6060369A
公开(公告)日：2000-05-09
申请号：US997318
申请日：1997-12-23
申请人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford
发明人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L21/823807
摘要： A integrated circuit transistor that has a high nitrogen concentration in the channel region and a method of making same are provided. A sacrificial oxide layer integrated with a nitrogen bearing species is grown on the substrate. A portion of the nitrogen bearing species diffuses into the substrate to form a nitrogen doped region. Nitrogen is implanted through the first oxide layer to increase the peak concentration of nitrogen in the nitrogen doped region. The sacrificial oxide layer is removed and a very thin gate oxide layer is formed. A gate, a source, and a drain are formed. The result is an integrated circuit transistor with a very thin gate oxide layer and a high peak concentration of nitrogen substantially at the Si--SiO.sub.2 interface.
摘要翻译：提供在通道区域中具有高氮浓度的集成电路晶体管及其制造方法。在基材上生长与含氮物质结合的牺牲氧化物层。含氮物质的一部分扩散到衬底中以形成氮掺杂区域。通过第一氧化物层注入氮气以增加氮掺杂区域中氮的峰值浓度。去除牺牲氧化物层并形成非常薄的栅极氧化物层。形成栅极，源极和漏极。结果是具有非常薄的栅极氧化物层和基本上在Si-SiO 2界面处的高的峰值浓度的集成电路晶体管。

46. 发明授权

US6057584A Semiconductor device having a tri-layer gate insulating dielectric 失效
标题翻译：具有三层栅极绝缘电介质的半导体器件
公开(公告)号：US6057584A
公开(公告)日：2000-05-02
申请号：US994302
申请日：1997-12-19
申请人： Mark I. Gardner , Mark C. Gilmer , H. Jim Fulford , Jack C. Lee
发明人： Mark I. Gardner , Mark C. Gilmer , H. Jim Fulford , Jack C. Lee
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66583 , H01L21/2822 , H01L21/28229
摘要： A semiconductor device having a gate insulating tri-layer includes a substrate, a nitrogen-containing layer disposed on the substrate, a first dielectric layer disposed over the nitrogen containing layer, a second dielectric layer disposed over the first dielectric layer, and a gate electrode disposed over the second dielectric layer. One of the first and second dielectric layers is formed using an oxide having a dielectric constant ranging from 4 to 100 and the other of the first and second dielectric layers is formed using an oxide having a higher dielectric constant ranging from 10 to 10,000.
摘要翻译：具有栅绝缘三层的半导体器件包括衬底，设置在衬底上的含氮层，设置在含氮层上的第一介电层，设置在第一介电层上的第二电介质层和栅电极设置在第二电介质层上。使用介电常数为4〜100的氧化物形成第一和第二电介质层中的一个，并且使用介电常数介于10〜10000的氧化物形成第一和第二电介质层中的另一个。

47. 发明授权

US6051876A Semiconductor device with a graded passivation layer 失效
标题翻译：具有渐变钝化层的半导体器件
公开(公告)号：US6051876A
公开(公告)日：2000-04-18
申请号：US2651
申请日：1998-01-05
申请人： Mark I. Gardner , Sey Ping Sun , Daniel Kadosh
发明人： Mark I. Gardner , Sey Ping Sun , Daniel Kadosh
IPC分类号： H01L23/31 , H01L23/48
CPC分类号： H01L23/3171 , H01L2924/0002 , H01L2924/13091
摘要： The formation of a graded passivation layer is disclosed. In one embodiment, a method includes four steps. In the first step, at least one transistor on a semiconductor substrate is provided. In the second step, at least one metallization layer is formed over the at least one transistor. In the third step, an oxide layer is deposited over the at least one metallization layer. Finally, in the fourth step, an ion implantation of a predetermined dopant is applied to create a graded passivation film over the at least one metallization layer.
摘要翻译：公开了渐变钝化层的形成。在一个实施例中，一种方法包括四个步骤。在第一步骤中，提供半导体衬底上的至少一个晶体管。在第二步骤中，在至少一个晶体管上形成至少一个金属化层。在第三步骤中，氧化物层沉积在至少一个金属化层上。最后，在第四步骤中，施加预定掺杂剂的离子注入以在至少一个金属化层上产生渐变钝化膜。

48. 发明授权

US6051865A Transistor having a barrier layer below a high permittivity gate dielectric 有权
标题翻译：具有位于高介电常数栅电介质下方的阻挡层的晶体管
公开(公告)号：US6051865A
公开(公告)日：2000-04-18
申请号：US189352
申请日：1998-11-09
申请人： Mark I. Gardner , Mark C. Gilmer , Derick J. Wristers
发明人： Mark I. Gardner , Mark C. Gilmer , Derick J. Wristers
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/28194 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L21/26506
摘要： A transistor and a method for making a transistor are described. Barrier species such as nitrogen may be introduced into a semiconductor substrate to form a barrier layer. A dielectric having a high dielectric constant, preferably a metal- and oxygen-bearing dielectric, may then be deposited upon the semiconductor substrate. The barrier layer preferably mitigates short channel effects and prevents dopant and/or metal atom migration into or out of the gate structure. The dielectric may be annealed in an oxygen-bearing atmosphere to passivate the dielectric material and to incorporate barrier species into the dielectric. Alternatively, the anneal may be performed in an inert atmosphere. Following deposition of a conductive gate material upon the dielectric, a gate conductor and gate dielectric may be patterned. Lightly doped drain impurity areas and/or source and drain impurity areas may then be formed in the semiconductor substrate.
摘要翻译：描述晶体管和制造晶体管的方法。可以将诸如氮的阻挡物质引入到半导体衬底中以形成阻挡层。然后可以在半导体衬底上沉积具有高介电常数的电介质，优选含金属和含氧电介质。阻挡层优选地减轻短沟道效应并防止掺杂物和/或金属原子迁移进入或离开栅极结构。电介质可以在含氧气氛中进行退火以钝化介电材料并将阻挡物质并入电介质中。或者，退火可以在惰性气氛中进行。在导电栅极材料沉积在电介质上之后，栅极导体和栅极电介质可以被图案化。然后可以在半导体衬底中形成轻掺杂漏极杂质区域和/或源极和漏极杂质区域。

49. 发明授权

US6049133A Semiconductor fabrication employing concurrent diffusion barrier and salicide formation 失效
标题翻译：采用同时扩散阻挡层和自对准硅化物形成的半导体制造
公开(公告)号：US6049133A
公开(公告)日：2000-04-11
申请号：US822121
申请日：1997-03-21
申请人： Fred N. Hause , Mark I. Gardner
发明人： Fred N. Hause , Mark I. Gardner
IPC分类号： H01C1/14 , H01C10/32 , H01C13/00 , H01C17/00 , H01L21/285 , H01L21/336 , H01L21/768 , H01L29/78
CPC分类号： H01L29/7833 , H01C10/32 , H01L21/28518 , H01L21/76841 , H01L21/76855 , H01L21/76856 , H01L29/665 , H01L29/6659
摘要： An integrated circuit fabrication process is provided in which a metal salicide and a diffusion barrier are formed concurrently. This process includes doping regions of a silicon substrate which are spaced apart by a polysilicon gate conductor, thereby forming source/drain junctions within the substrate upper surface. Oxide spacers are located on opposite sidewall surfaces of the gate conductor. The resulting semiconductor topography is then placed within a chamber having a pressurized and heated nitrogen ambient. A metal, i.e., titanium is deposited upon the semiconductor topography, and then annealing of the metal occurs. The titanium metal reacts with silicon at interfaces not containing nitrogen atoms, i.e., exclusive of the oxide spacers, to form titanium salicide. Concurrent with this reaction is the formation of titanium nitride upon the titanium metal. Finally, aluminum is deposited upon the titanium nitride to complete metallization. The titanium nitride diffusion barrier prevents aluminum spiking of the doped junctions below.
摘要翻译：提供了同时形成金属硅化物和扩散阻挡层的集成电路制造工艺。该工艺包括由多晶硅栅极导体隔开的硅衬底的掺杂区域，从而在衬底上表面内形成源极/漏极结。氧化物间隔物位于栅极导体的相对侧壁表面上。然后将所得半导体形貌放置在具有加压和加热的氮气环境的室内。在半导体形貌上沉积金属，即钛，然后发生金属的退火。钛金属在不含氮原子的界面（即不包括氧化物间隔物）与硅反应形成硅化硅。与此反应同时在钛金属上形成氮化钛。最后，铝沉积在氮化钛上以完成金属化。氮化钛扩散阻挡层阻止下述掺杂结的铝尖峰。

50. 发明授权

US6046471A Ultra shallow junction depth transistors 失效
标题翻译：超浅结深度晶体管
公开(公告)号：US6046471A
公开(公告)日：2000-04-04
申请号：US744405
申请日：1996-11-07
申请人： Mark I. Gardner , Fred N. Hause , Daniel Kadosh
发明人： Mark I. Gardner , Fred N. Hause , Daniel Kadosh
IPC分类号： H01L21/265 , H01L21/336 , H01L31/119
CPC分类号： H01L29/66575 , H01L21/2652
摘要： A shallow junction MOS transistor comprising a semiconductor substrate having an upper region that includes a first and a second lightly doped region laterally displaced on either side of the channel region. The first and second lightly doped regions extend to a junction depth below the upper surface of the semiconductor substrate. A first and a second lightly doped impurity distribution are located within the first and second source/drain regions of the semiconductor substrate. The shallow junction transistor further includes a gate dielectric formed on an upper surface of the channel region of the semiconductor substrate. A conductive gate that includes a first and a second sidewall is formed on the gate dielectric. A gate insulator is formed in contact with the first and second sidewalls of the conductive gate. First and second source/drain structures are formed above the upper surface of the semiconductor substrate. The first and second source/drain structures are laterally displaced over the first and second lightly doped regions of the semiconductor substrate.
摘要翻译：一种浅结MOS晶体管，包括具有上部区域的半导体衬底，所述上部区域包括在沟道区域的任一侧上横向移位的第一和第二轻掺杂区域。第一和第二轻掺杂区域延伸到半导体衬底的上表面下方的结深度。第一和第二轻掺杂杂质分布位于半导体衬底的第一和第二源极/漏极区域内。浅结晶体管还包括形成在半导体衬底的沟道区的上表面上的栅极电介质。包括第一和第二侧壁的导电栅极形成在栅极电介质上。栅极绝缘体形成为与导电栅极的第一和第二侧壁接触。第一和第二源极/漏极结构形成在半导体衬底的上表面之上。第一和第二源极/漏极结构在半导体衬底的第一和第二轻掺杂区域上横向移位。

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