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    • 42. 发明授权
      US07985651B2 Method of fabricating semiconductor device having differential gate dielectric layer and related device 有权
    • Method of fabricating semiconductor device having differential gate dielectric layer and related device
    • 制造具有差分栅极介电层的半导体器件及其相关器件的方法
    • US07985651B2
    • 2011-07-26
    • US12318384
    • 2008-12-29
    • Joo-Young Lee , Jin-Woo Lee
    • Joo-Young Lee , Jin-Woo Lee
    • H01L21/336
    • H01L29/66621 , H01L21/26586 , H01L21/2822 , H01L29/42368
    • A semiconductor device and method of fabricating a semiconductor device are provided. The method includes forming a gate trench in a semiconductor substrate to define source/drain regions. The source/drain regions are separated from each other by the gate trench, and the semiconductor substrate is exposed through the gate trench. The semiconductor substrate has impurities of a first conductivity type. The source/drain regions have impurities of a second conductivity type different from the first conductivity type. The concentration of the second conductivity type impurities increases as the impurities approach the surfaces of the source/drain regions. A differential gate dielectric layer is formed along the surfaces of the source/drain regions and the semiconductor substrate exposed through the gate trench. A gate electrode filling the gate trench is formed. The differential gate dielectric layer has a first thickness between the gate electrode and the semiconductor substrate and has a second thickness greater than the first thickness between the gate electrode and the source/drain regions.
    • 提供一种制造半导体器件的半导体器件和方法。 该方法包括在半导体衬底中形成栅极沟槽以限定源极/漏极区域。 源极/漏极区域通过栅极沟槽彼此分离，并且半导体衬底通过栅极沟槽暴露。 半导体衬底具有第一导电类型的杂质。 源极/漏极区域具有不同于第一导电类型的第二导电类型的杂质。 随着杂质接近源极/漏极区域的表面，第二导电型杂质的浓度增加。 沿着源极/漏极区域和通过栅极沟槽暴露的半导体衬底的表面形成差分栅极介电层。 形成填充栅极沟槽的栅电极。 差分栅极介电层在栅电极和半导体衬底之间具有第一厚度，并且具有大于栅极电极和源极/漏极区域之间的第一厚度的第二厚度。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 45. 发明申请
      US20090176342A1 Method of fabricating semiconductor device having deifferential gate dielectric layer and related device 有权
    • Method of fabricating semiconductor device having deifferential gate dielectric layer and related device
    • 制造具有栅极绝缘层的半导体器件的方法及其相关器件
    • US20090176342A1
    • 2009-07-09
    • US12318384
    • 2008-12-29
    • Joo-Young Lee , Jin-Woo Lee
    • Joo-Young Lee , Jin-Woo Lee
    • H01L21/336
    • H01L29/66621 , H01L21/26586 , H01L21/2822 , H01L29/42368
    • A semiconductor device and method of fabricating a semiconductor device are provided. The method includes forming a gate trench in a semiconductor substrate to define source/drain regions. The source/drain regions are separated from each other by the gate trench, and the semiconductor substrate is exposed through the gate trench. The semiconductor substrate has impurities of a first conductivity type. The source/drain regions have impurities of a second conductivity type different from the first conductivity type. The concentration of the second conductivity type impurities increases as the impurities approach the surfaces of the source/drain regions. A differential gate dielectric layer is formed along the surfaces of the source/drain regions and the semiconductor substrate exposed through the gate trench. A gate electrode filling the gate trench is formed. The differential gate dielectric layer has a first thickness between the gate electrode and the semiconductor substrate and has a second thickness greater than the first thickness between the gate electrode: and the source/drain regions.
    • 提供一种制造半导体器件的半导体器件和方法。 该方法包括在半导体衬底中形成栅极沟槽以限定源极/漏极区域。 源极/漏极区域通过栅极沟槽彼此分离，并且半导体衬底通过栅极沟槽暴露。 半导体衬底具有第一导电类型的杂质。 源极/漏极区域具有不同于第一导电类型的第二导电类型的杂质。 随着杂质接近源极/漏极区域的表面，第二导电型杂质的浓度增加。 沿着源极/漏极区域和通过栅极沟槽暴露的半导体衬底的表面形成差分栅极介电层。 形成填充栅极沟槽的栅电极。 差分栅极介电层在栅电极和半导体衬底之间具有第一厚度，并且具有大于栅极电极与源极/漏极区域之间的第一厚度的第二厚度。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 49. 发明授权
      US5935875A Dual insulating layer methods for forming integrated circuit gates and conductive contacts 失效
    • Dual insulating layer methods for forming integrated circuit gates and conductive contacts
    • 用于形成集成电路栅极和导电触点的双重绝缘层方法
    • US5935875A
    • 1999-08-10
    • US785091
    • 1997-01-21
    • Joo-young Lee
    • Joo-young Lee
    • H01L27/108 , H01L21/8234 , H01L21/8242 , H01L21/302
    • H01L27/10873 , H01L21/8234 , H01L27/10894 , H01L27/10852
    • A second insulating layer is used to mask a first insulating layer on a second gate electrode, during fabrication of a conductive contact adjacent a first gate electrode which is spaced apart from the second gate electrode. By using the second insulating layer as a sacrificial insulating layer during etching of the conductive contact, thinning of the first insulating layer on the second gate electrode may be prevented. In particular, first and second spaced apart gate electrodes are formed on an integrated circuit surface. The first and second spaced apart gate electrodes include first and second sidewalls, respectively. The first insulating layer and the second insulating layer are formed on the integrated circuit surface, including on the first and second gate electrodes. The second insulating layer is removed from the first gate. The first insulating layer is etched on the first gate to thereby form first spacers on the first sidewalls. A conductive contact is formed on the integrated circuit face, adjacent the first gate electrode and extending onto the first sidewall. The second insulating layer is removed from on the second gate and the first insulating layer is etched on the second gate, to thereby form second spacers on the second sidewalls.
    • 在与第二栅电极间隔开的第一栅极附近的导电接触的制造期间，第二绝缘层用于掩蔽第二栅电极上的第一绝缘层。 通过在导电接触的蚀刻期间使用第二绝缘层作为牺牲绝缘层，可以防止第二栅电极上的第一绝缘层的薄化。 特别地，第一和第二间隔开的栅电极形成在集成电路表面上。 第一和第二间隔开的栅电极分别包括第一和第二侧壁。 第一绝缘层和第二绝缘层形成在集成电路表面上，包括在第一和第二栅电极上。 第二绝缘层从第一栅极去除。 在第一栅极上蚀刻第一绝缘层，从而在第一侧壁上形成第一间隔物。 导电接触形成在集成电路面上，与第一栅电极相邻并延伸到第一侧壁上。 从第二栅极上去除第二绝缘层，在第二栅极上蚀刻第一绝缘层，从而在第二侧壁上形成第二间隔物。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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