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41. 发明授权

US07205199B2 Method of forming a recess channel trench pattern, and fabricating a recess channel transistor 有权
标题翻译：形成凹槽沟槽图案的方法，以及制造凹槽通道晶体管
公开(公告)号：US07205199B2
公开(公告)日：2007-04-17
申请号：US10917615
申请日：2004-08-13
申请人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
发明人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

42. 发明申请

US20050230734A1 Field effect transistors having trench-based gate electrodes and methods of forming same 审中-公开
标题翻译：具有沟槽栅电极的场效应晶体管及其形成方法
公开(公告)号：US20050230734A1
公开(公告)日：2005-10-20
申请号：US11109422
申请日：2005-04-19
申请人： Jae-Kyu Ha , Jong-Chul Park
发明人： Jae-Kyu Ha , Jong-Chul Park
IPC分类号： H01L21/28 , H01L21/336 , H01L21/76 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L27/10817 , H01L27/10814 , H01L27/10823 , H01L27/10876
摘要： Embodiments of the invention include dynamic random access memory (DRAM) devices that utilize field effect transistors with trench-based gate electrodes. In these devices, a semiconductor substrate is provided having an isolation trench therein. This isolation trench is formed in a first portion of the semiconductor substrate. An electrically insulating liner is provided on a bottom and sidewalls of the isolation trench. The isolation trench is also filled with field oxide region, which extends on the electrically insulating liner. A field effect transistor is also provided in the semiconductor substrate. This transistor includes a gate electrode trench in a second portion of the semiconductor substrate and a gate insulating layer that lines a bottom and sidewalls of the gate electrode trench. A gate electrode is provided in the gate electrode trench. The gate electrode contacts the electrically insulating liner in the isolation trench and the gate insulating layer. Source and drain regions extend in the semiconductor substrate and adjacent the gate electrode.
摘要翻译：本发明的实施例包括使用具有基于沟槽的栅电极的场效应晶体管的动态随机存取存储器（DRAM）器件。在这些器件中，提供了在其中具有隔离沟槽的半导体衬底。该隔离沟槽形成在半导体衬底的第一部分中。电绝缘衬垫设置在隔离沟槽的底部和侧壁上。隔离沟槽还填充有在电绝缘衬垫上延伸的场氧化物区域。在半导体衬底中还提供场效应晶体管。该晶体管包括在半导体衬底的第二部分中的栅极电极沟槽和对栅极电极沟槽的底部和侧壁进行排列的栅极绝缘层。栅电极设置在栅电极沟槽中。栅电极接触隔离沟槽和栅极绝缘层中的电绝缘衬垫。源极和漏极区域在半导体衬底中延伸并且与栅电极相邻。

43. 发明申请

US20050145338A1 Shower head of a wafer treatment apparatus having a gap controller 审中-公开
标题翻译：具有间隙控制器的晶片处理装置的花洒头
公开(公告)号：US20050145338A1
公开(公告)日：2005-07-07
申请号：US11057752
申请日：2005-02-15
申请人： Jong-chul Park , Dong-hyun Kim , O-ik Kwon , Hye-jin Jo
发明人： Jong-chul Park , Dong-hyun Kim , O-ik Kwon , Hye-jin Jo
IPC分类号： H01L21/3065 , C23C16/44 , C23C16/455 , H01L21/00 , C23F1/00
CPC分类号： C23C16/45565 , C23C16/45589 , H01L21/67017
摘要： A shower head for adjusting distribution of a reactant gas in a process region of a semiconductor manufacturing reaction chamber, wherein a top plate has a gas port for introducing the reactant gas into the reaction chamber; a face plate, having through holes, disposed opposite the process region; a first baffle plate, having through holes, disposed between the top plate and the face plate and capable of moving up or down, wherein the first baffle plate has a top surface that defines a first gap for forming a first lateral flow passage; a second baffle plate, having through holes, disposed between the first baffle plate and the face plate and capable of moving up or down, wherein the second baffle plate has a top surface that defines a second gap for forming a second lateral flow passage; and a gap controller for determining widths of the first and second gaps.
摘要翻译：一种用于调整半导体制造反应室的处理区域中的反应气体的分布的喷头，其中顶板具有用于将反应气体引入反应室的气体口; 具有与所述处理区域相对设置的通孔的面板; 第一挡板，具有设置在所述顶板和所述面板之间并且能够上下移动的通孔，其中所述第一挡板具有限定用于形成第一侧流通道的第一间隙的顶表面; 第二挡板，具有设置在第一挡板和面板之间并且能够上下移动的通孔，其中第二挡板具有限定用于形成第二侧流通道的第二间隙的顶表面; 以及用于确定第一和第二间隙的宽度的间隙控制器。

44. 发明申请

US20050077568A1 Method of forming a recess channel trench pattern, and fabricating a recess channel transistor 有权
标题翻译：形成凹槽沟槽图案的方法，以及制造凹槽通道晶体管
公开(公告)号：US20050077568A1
公开(公告)日：2005-04-14
申请号：US10917615
申请日：2004-08-13
申请人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
发明人： Jong-Chul Park , Yong-Sun Ko , Tae-Hyuk Ahn
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/423 , H01L29/76 , H01L21/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

45. 发明申请

US20050035427A1 MOS transistor with recessed gate and method of fabricating the same 失效
标题翻译：具有凹陷栅极的MOS晶体管及其制造方法
公开(公告)号：US20050035427A1
公开(公告)日：2005-02-17
申请号：US10884223
申请日：2004-07-01
申请人： Jong-Chul Park , Jong-Heui Song
发明人： Jong-Chul Park , Jong-Heui Song
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L29/78 , H01L21/76 , H01L29/12
CPC分类号： H01L29/66621 , H01L21/823437 , H01L21/823481 , H01L21/823487 , H01L27/10876 , H01L29/66537 , H01L29/7835
摘要： A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent the negatively slopped sidewall of the trench isolation layer.
摘要翻译：具有凹陷栅极的MOS晶体管及其制造方法：MOS晶体管包括半导体衬底和位于半导体衬底的用于限定有源区的预定区域中的沟槽隔离层。沟槽隔离层在至少其下侧壁上具有负斜率。凹入栅极位于有源区的预定区域中，并且凹入栅极的底表面邻近沟槽隔离层的负斜面侧壁放置。

46. 发明申请

US20170338408A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE 审中-公开
公开(公告)号：US20170338408A1
公开(公告)日：2017-11-23
申请号：US15675089
申请日：2017-08-11
申请人： Jong-Chul PARK , Byoung-Jae BAE , Shin-Jae KANG , Young-Seok CHOI
发明人： Jong-Chul PARK , Byoung-Jae BAE , Shin-Jae KANG , Young-Seok CHOI
IPC分类号： H01L43/12 , H01L43/08 , H01L27/22
CPC分类号： H01L43/12 , G11C11/161 , H01L27/228 , H01L43/08
摘要： In a method of manufacturing an MRAM device, a lower electrode and a preliminary first free layer pattern sequentially stacked are formed on a substrate. An upper portion of the preliminary first free layer pattern is removed to form a first free layer pattern. A second free layer and a tunnel barrier layer are sequentially formed on the first free layer pattern. The second free layer is partially oxidized to form a second free layer pattern. A fixed layer structure is formed on the tunnel barrier layer.

47. 发明申请

US20170162270A1 NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM, METHOD OF OPERATING NONVOLATILE MEMORY DEVICE, AND METHOD OF OPERATING MEMORY SYSTEM 有权
公开(公告)号：US20170162270A1
公开(公告)日：2017-06-08
申请号：US15281837
申请日：2016-09-30
申请人： JONG-CHUL PARK , HYUN-YOUNG YOO , SANG-SOO PARK
发明人： JONG-CHUL PARK , HYUN-YOUNG YOO , SANG-SOO PARK
IPC分类号： G11C16/34 , G11C16/26 , G11C16/10 , G11C16/04
CPC分类号： G11C16/3431 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/021 , G11C29/028
摘要： A method of operating a nonvolatile memory device that includes a three-dimensional (3D) memory cell array is provided as follows. A first read operation is performed on first memory cells connected to a first word line by using a first read voltage level. A read retry operation is, if the first read operation fails, performed on the first memory cells so that a read retry voltage level is set to a second read voltage level. A read offset table is determined based on a difference between the first read voltage level and the second read voltage level. The read offset table stores a plurality of read voltage offsets. A second read operation is performed on second memory cells connected to a second word line by using a third read voltage level determined using the read offset table.

48. 发明申请

US20160118578A1 MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：磁记忆体装置及其制造方法
公开(公告)号：US20160118578A1
公开(公告)日：2016-04-28
申请号：US14825161
申请日：2015-08-12
申请人： Jong Chul PARK , Shin Jae KANG
发明人： Jong Chul PARK , Shin Jae KANG
IPC分类号： H01L43/12 , G11C11/16 , H01L43/10 , H01L27/22 , H01L43/02 , H01L43/08
CPC分类号： H01L43/12 , G11C11/161 , H01L27/228 , H01L43/08
摘要： A method of manufacturing a magnetic memory device includes forming a lower magnetic layer, a tunnel barrier layer, and an upper magnetic layer on a substrate, forming a magnetic tunnel junction (MTJ) pattern by patterning the lower magnetic layer, the tunnel barrier layer, and the upper magnetic layer, and irradiating a side wall of the MTJ pattern using a beam including an oxygen ion, wherein, in the forming of the MTJ pattern, a metal redeposition material covering the side wall of the MTJ pattern is formed and the beam is radiated to the metal redeposition material.
摘要翻译：一种制造磁存储器件的方法包括在衬底上形成下磁层，隧道势垒层和上磁层，通过图形化下磁层，隧道势垒层和隧道势垒层形成磁隧道结（MTJ）和上磁性层，并且使用包括氧离子的束照射MTJ图案的侧壁，其中在形成MTJ图案时，形成覆盖MTJ图案的侧壁的金属再沉积材料，并且光束被辐射到金属再沉积材料。

49. 发明授权

US08518335B2 System for preparing silica aerogel powder 有权
标题翻译：制备二氧化硅气凝胶粉体系
公开(公告)号：US08518335B2
公开(公告)日：2013-08-27
申请号：US13161989
申请日：2011-06-16
申请人： Young Chul Joung , Myung Je Roe , Young Jong Yoo , Jong Chul Park , Hee Jung Choi , Min Woo Kim
发明人： Young Chul Joung , Myung Je Roe , Young Jong Yoo , Jong Chul Park , Hee Jung Choi , Min Woo Kim
IPC分类号： B01J19/00 , C01B33/12
CPC分类号： C01B33/1585 , B01J19/0066 , B01J19/24 , B01J2219/00006 , B01J2219/00083 , C01P2006/12 , F26B11/16
摘要： A system for preparing silica aerogel powders. The system includes a material supplier, a mixer, a drier and a recoverer. The material supplier transmitting de-ionized water, water glass, an organosilane compound, an inorganic acid and at least one organic solvent. Some of organic solvents are mixed and transmitted to the mixer and tramining organic solvent is transmitted to the mixer. The mixer mixes the materials transmitted from the material supplier so as to generate silica hydrogel. The drier dries the silica hydrogel so as to generate silica aerogel powders. The recoverer recovers some vaporized materials of the materials used in the mixer and the drier.
摘要翻译：一种制备二氧化硅气凝胶粉末的系统。该系统包括材料供应商，搅拌机，干燥机和回收机。发送去离子水，水玻璃，有机硅烷化合物，无机酸和至少一种有机溶剂的材料供应商。将一些有机溶剂混合并传输到混合器中，并将有机溶剂的有机溶剂传输到混合器中。混合器将从材料供应商传送的材料混合以产生二氧化硅水凝胶。干燥器干燥二氧化硅水凝胶以产生二氧化硅气凝胶粉末。回收器回收混合器和干燥器中使用的材料的一些汽化材料。

50. 发明授权

US08445379B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08445379B2
公开(公告)日：2013-05-21
申请号：US13271535
申请日：2011-10-12
申请人： Jong-chul Park , Sang-sup Jeong , Bok-yeon Won
发明人： Jong-chul Park , Sang-sup Jeong , Bok-yeon Won
IPC分类号： H01L21/44
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/32139 , H01L21/76816 , H01L27/0207 , H01L27/10855 , H01L27/10888
摘要： A method of manufacturing a semiconductor device including a plurality of hole patterns is disclosed. The method includes: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns where the plurality of first line patterns and the plurality of second line patterns cross each other.
摘要翻译：公开了一种制造包括多个孔图案的半导体器件的方法。该方法包括：形成多个第一线图案和沿第一方向延伸的多个第一空间图案; 在所述多个第一线图案和所述多个第一空间图案上形成多个第二线图案和沿第二方向延伸的多个第二空间图案; 形成多个第一孔图案，其中所述多个第一空间图案和所述多个第二空间图案彼此交叉; 以及形成多个第一孔图案，其中所述多个第一线条图案和所述多个第二线条图案彼此交叉。

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