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41. 发明申请

US20090027065A1 Wordline-To-Bitline Output Timing Ring Oscillator Circuit for Evaluating Storage Array Performance 失效
标题翻译：用于评估存储阵列性能的字线到位线输出定时环形振荡器电路
公开(公告)号：US20090027065A1
公开(公告)日：2009-01-29
申请号：US11781994
申请日：2007-07-24
申请人： Jente B. Kuang , Jerry C. Keo , Hung C. Ngo , Kevin J. Nowka , Liang-Teck Pang , Jayakumaran Sivagnaname
发明人： Jente B. Kuang , Jerry C. Keo , Hung C. Ngo , Kevin J. Nowka , Liang-Teck Pang , Jayakumaran Sivagnaname
IPC分类号： G01R27/28
CPC分类号： G11C29/50 , G01R31/31937 , G11C29/50012 , G11C2029/1202 , G11C2029/1204
摘要： A wordline-to-bitline timing ring oscillator circuit for evaluating storage cell access time provides data on internal bitline access timing, and in particular the total wordline select-to-bitline read output timing. Columns of a storage array are connected in a ring, forming a ring oscillator. The bitline read circuit output of each column is connected to a wordline select input of a next column, with a net inversion around the ring, so that a ring oscillator is formed. The period of oscillation of the ring oscillator is determined by the total wordline select-to-bitline read circuit output timing for a first phase and the pre-charge interval time for the other phase, with the bitline read timing dominating. The circuit may be applied both to small-signal storage arrays, with the sense amplifier timing included within the ring oscillator period, or to large-signal storage arrays, with the read evaluate circuit timing included.
摘要翻译：用于评估存储单元访问时间的字线到位线定时环形振荡器电路提供关于内部位线访问定时的数据，特别是总字线选择到位线读出输出定时。存储阵列的列以环形连接，形成环形振荡器。每列的位线读取电路输出连接到下一列的字线选择输入，环绕环反转，从而形成环形振荡器。环形振荡器的振荡周期由第一相的总字线选择到位线读取电路输出定时和另一相的预充电间隔时间决定，而位线读取时序主导。该电路可以应用于小信号存储阵列，其中包括在环形振荡器周期内的读出放大器定时，或者包括读取评估电路时序的大信号存储阵列。

42. 发明授权

US07409305B1 Pulsed ring oscillator circuit for storage cell read timing evaluation 有权
标题翻译：脉冲环形振荡电路用于存储单元读取时序评估
公开(公告)号：US07409305B1
公开(公告)日：2008-08-05
申请号：US11682542
申请日：2007-03-06
申请人： Gary D. Carpenter , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G06F3/01
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A methor for storage cell read timing evaluation provides read strength information by using a pulsed ring oscillator. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译：用于存储单元读取定时评估的方法通过使用脉冲环形振荡器来提供读取强度信息。脉冲发生器耦合到待测量的存储单元连接到的位线。因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。读取电流是电流之间的差异。

43. 发明授权

US07408829B2 Methods and arrangements for enhancing power management systems in integrated circuits 有权
标题翻译：集成电路中增强电源管理系统的方法和安排
公开(公告)号：US07408829B2
公开(公告)日：2008-08-05
申请号：US11352699
申请日：2006-02-13
申请人： Jente B. Kuang , Hung Cai Ngo
发明人： Jente B. Kuang , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.
摘要翻译：本文提供了为集成电路配置电源管理系统的方法和布置。功能上不同或具有互斥和/或准互斥（ME / QME）操作模式（即交替或部分重叠占空比）的一组IC组件可以由单个功率单元供电。集成电路设计工具可以识别具有ME / QME操作模式的集成电路设计中的组件。这些电池可以彼此靠近并置，并且功率管理系统组件可以放置在该区域中，使得多个信号处理单元可以共享单个电源线和单个功率单元。这种配置可以大大减小用于集成电路的电力管理系统的尺寸。

44. 发明申请

US20080130387A1 METHOD FOR EVALUATING MEMORY CELL PERFORMANCE 失效
标题翻译：评估记忆体性能的方法
公开(公告)号：US20080130387A1
公开(公告)日：2008-06-05
申请号：US11741187
申请日：2007-04-27
申请人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50012 , G11C2029/1204
摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
摘要翻译：用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作。该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。弱写入条件和/或弱写入条件可以通过选择性加载来测量。

45. 发明授权

US07372305B1 Scannable dynamic logic latch circuit 失效
标题翻译：可扫描动态逻辑锁存电路
公开(公告)号：US07372305B1
公开(公告)日：2008-05-13
申请号：US11554685
申请日：2006-10-31
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K19/096
CPC分类号： H03K19/096 , G01R31/318541
摘要： A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to the dynamic node of the dynamic logic gate. A scan clock and a normal clock determine whether the logic circuitry is in the normal logic mode or in the scan test mode. A static output latch has at least one input that is responsive logic state of a dynamic node. The evaluated state of the dynamic node is set by either the logic tree of the dynamic logic gate or the scan pull-down logic tree of the scan circuitry in response to the logic state of the scan clock or the normal clock.
摘要翻译：可扫描的锁存器包含具有至少一个具有执行正常布尔逻辑运算的逻辑树的动态逻辑门的逻辑前端。动态逻辑门被组合成扫描下拉逻辑树，其被耦合到扫描保持锁存器输出和动态逻辑门的动态节点。扫描时钟和正常时钟确定逻辑电路是处于正常逻辑模式还是处于扫描测试模式。静态输出锁存器具有至少一个作为动态节点的响应逻辑状态的输入。响应于扫描时钟或正常时钟的逻辑状态，动态节点的评估状态由动态逻辑门的逻辑树或扫描电路的扫描下拉逻辑树来设置。

46. 发明申请

US20080100344A1 SCANNABLE DYNAMIC LOGIC LATCH CIRCUIT 失效
标题翻译： SCANNABLE动态逻辑锁存电路
公开(公告)号：US20080100344A1
公开(公告)日：2008-05-01
申请号：US11554685
申请日：2006-10-31
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K19/096
CPC分类号： H03K19/096 , G01R31/318541
摘要： A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to the dynamic node of the dynamic logic gate. A scan clock and a normal clock determine whether the logic circuitry is in the normal logic mode or in the scan test mode. A static output latch has at least one input that is responsive logic state of a dynamic node. The evaluated state of the dynamic node is set by either the logic tree of the dynamic logic gate or the scan pull-down logic tree of the scan circuitry in response to the logic state of the scan clock or the normal clock.
摘要翻译：可扫描的锁存器包含具有至少一个具有执行正常布尔逻辑运算的逻辑树的动态逻辑门的逻辑前端。动态逻辑门被组合成扫描下拉逻辑树，其被耦合到扫描保持锁存器输出和动态逻辑门的动态节点。扫描时钟和正常时钟确定逻辑电路是处于正常逻辑模式还是处于扫描测试模式。静态输出锁存器具有至少一个作为动态节点的响应逻辑状态的输入。响应于扫描时钟或正常时钟的逻辑状态，动态节点的评估状态由动态逻辑门的逻辑树或扫描电路的扫描下拉逻辑树来设置。

47. 发明授权

US06940312B2 Low switching power limited switch dynamic logic 失效
标题翻译：低开关功率限制开关动态逻辑
公开(公告)号：US06940312B2
公开(公告)日：2005-09-06
申请号：US10733936
申请日：2003-12-11
申请人： Hung C. Ngo , Jente B. Kuang
发明人： Hung C. Ngo , Jente B. Kuang
IPC分类号： H03K3/356 , H03K19/096
CPC分类号： H03K19/0963 , H03K3/356121
摘要： An LSDL circuit is improved by having the data input function to control the pre-charging of the dynamic node. The clock signal no longer is coupled to the P channel FET used to pre-charge the dynamic node. Additionally an N channel FET (NFET) is added in parallel with the NFET coupled to the clock for evaluating the dynamic node. This NFET assures the dynamic node does not float when the data input is a logic one and the clock is a logic zero.
摘要翻译：通过具有数据输入功能来控制动态节点的预充电来改进LSDL电路。时钟信号不再耦合到用于对动态节点预充电的P沟道FET。此外，与耦合到时钟的NFET并联添加N沟道FET（NFET）以评估动态节点。该NFET保证当数据输入为逻辑1且时钟为逻辑0时，动态节点不浮动。

48. 发明授权

US06872991B1 Low gate-leakage virtual rail circuit 失效
标题翻译：低栅极泄漏虚拟轨道电路
公开(公告)号：US06872991B1
公开(公告)日：2005-03-29
申请号：US10840708
申请日：2004-05-06
申请人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka
发明人： Hung C. Ngo , Jente B. Kuang , Kevin J. Nowka
IPC分类号： H03K19/00 , H01L27/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H03K19/0016
摘要： Circuits within a logic domain use partitioned power supply buses. Selected of the power supply buses are coupled to the power supply voltage potentials with electronic switches with gradated conductivity and leakage current. When the circuits are actively switching during a logic operation, the power supply voltage potentials are coupled to the buses with maximum conductivity. At predetermined times later, selected of the electronic switches are switched OFF to reduce leakage current. Lower conductivity and thus lower leakage switches remain ON to ensure corresponding logic states are maintained during a controlled low leakage time period. Various logic configurations are used to switch OFF high leakage devices.
摘要翻译：逻辑域内的电路使用分区电源总线。选择的电源总线通过具有梯度电导率和漏电流的电子开关耦合到电源电压电位。当电路在逻辑运行期间主动切换时，电源电压电位以最大导电率耦合到总线。在预定时间后，选择的电子开关被切断以减少漏电流。较低的电导率和因此较低的漏电开关保持ON，以确保在受控的低泄漏时间段期间保持相应的逻辑状态。各种逻辑配置用于关闭高泄漏设备。

49. 发明授权

US5872733A Ramp-up rate control circuit for flash memory charge pump 失效
标题翻译：闪存充电泵的升压速率控制电路
公开(公告)号：US5872733A
公开(公告)日：1999-02-16
申请号：US730628
申请日：1996-10-21
申请人： Taqi Nasser Buti , Louis Lu-Chen Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary Joseph Saccamango , Hyun Jong Shin
发明人： Taqi Nasser Buti , Louis Lu-Chen Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary Joseph Saccamango , Hyun Jong Shin
IPC分类号： G11C16/30 , H03K5/04 , H03F3/16 , H03L7/00
CPC分类号： G11C16/30 , H03K5/04
摘要： An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current. In one embodiment, the apparatus comprises a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output. The body is adapted for connection to the charge pump output. The apparatus further comprises a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input. The control circuit provides a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor. The flow of current through the current path of the current bleeder path is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. Other embodiments of the apparatus of the present invention are described herein.
摘要翻译：一种用于控制具有提供输出电压和输出电流的输出的电荷泵的上升速率的装置。在一个实施例中，该装置包括具有输入，适于连接到地电势的输出和至少一个具有栅极，源极，漏极和主体的晶体管的电流泄放电路，并且限定源极和漏极之间的至少一个电流路径形成输入和输出之间的当前路径。主体适用于连接到电荷泵输出。该装置还包括具有适于连接到电荷泵输出的输入端的控制电路和连接到泄放电路输入端的输出端。控制电路为电流放电电路的输入提供电压电位，以控制电流放电电路晶体管的栅极 - 源极电压。通过电流泄放路径的电流路径的电流流动是电荷泵输出的大小和泄放电路晶体管的栅极 - 源极电压的函数。本文描述了本发明装置的其它实施例。

50. 发明授权

US08555119B2 Test structure for characterizing multi-port static random access memory and register file arrays 失效
标题翻译：用于表征多端口静态随机存取存储器和寄存器文件阵列的测试结构
公开(公告)号：US08555119B2
公开(公告)日：2013-10-08
申请号：US13459932
申请日：2012-04-30
申请人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
发明人： Leland Chang , Jente B. Kuang , Robert K. Montoye , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C8/16 , G11C29/32 , G11C29/50 , G11C29/50012
摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.
摘要翻译：用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

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