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41. 发明授权

US06760896B2 Process layout of buffer modules in integrated circuits 失效
公开(公告)号：US06760896B2
公开(公告)日：2004-07-06
申请号：US10254607
申请日：2002-09-25
申请人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
发明人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A bus is defined on a core of an integrated circuit. Routing lines are defined through the core, and net wires are routed through the core along respective routing lines. Buffer columns are defined in the core across a plurality of nets, and buffers are placed in the buffer columns so that an input and output to a respective buffer are on different routing lines. The buffers have at least one free routing line and the net wires are redistribution across the buffer so that (i) the net wire to be buffered is re-routed to the input and output of the buffer, (ii) the net wires on routing lines containing the input and output of the buffer are re-routed to the routing line of the net wire to be buffered and the free routing line, and (iii) all other net wires are routed along their respective routing lines.

42. 发明授权

US06637016B1 Assignment of cell coordinates 有权
标题翻译：分配单元坐标
公开(公告)号：US06637016B1
公开(公告)日：2003-10-21
申请号：US09841824
申请日：2001-04-25
申请人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
发明人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method for selectively placing cells of an application-specific integrated circuit on a substrate surface, including the steps of defining a grid covering a substrate surface, assigning cells to the grid to provide old x and y coordinates of the cells relative to the grid, grouping the cells by function to provide functional regions within the grid, determining a density map of the surface of the substrate in all the functional regions within the grid, determining free space of the grid on the surface of the substrate relative to the density map, and assigning new cells to the free space of the grid on the substrate surface to provide an application specific integrated circuit. Use of the method provides improved layout of an integrated circuit with minimal cell congestion or overlapping.
摘要翻译：一种用于选择性地将专用集成电路的单元放置在衬底表面上的方法，包括以下步骤：限定覆盖衬底表面的栅格，将单元分配给栅格以提供单元相对于栅格的旧x和y坐标，通过功能对细胞进行分组以在网格内提供功能区域，确定网格内所有功能区域中基底表面的密度图，确定基底表面上的网格相对于密度图的自由空间，并将新的单元分配给衬底表面上的栅格的自由空间以提供专用集成电路。该方法的使用提供了具有最小的信元拥塞或重叠的集成电路的改进布局。

43. 发明授权

US06557144B1 Netlist resynthesis program based on physical delay calculation 失效
标题翻译：基于物理延迟计算的网表再合成程序
公开(公告)号：US06557144B1
公开(公告)日：2003-04-29
申请号：US09737239
申请日：2000-12-14
申请人： Aiguo Lu , Ivan Pavisic , Pedja Raspopovic
发明人： Aiguo Lu , Ivan Pavisic , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5072
摘要： A computer program that improves a netlist of logic nodes and physical placement for an IC. The program (a) identifies critical nodes based on delay information calculated from the physical placement. Then the program (b) selects a set of critical nodes and optimally collapses their critical fan-ins and part of the non-critical fan-ins based on their Boolean relationship, which, includes at least one critical node. After that, the program (c) remaps the collapsed sub-netlist by covering its subject graph with an optimal pattern graph, and dynamically estimates and updates the fanout loads. The program returns to step (b) if the remapped sub-netlist is unacceptable, and returns to step (a) after updating the delay information and coordinates of newly mapped gates if the remapped sub-netlist is acceptable. The program exits at step (a) when no more critical nodes are identified at step (a).
摘要翻译：一种改进逻辑节点网表和IC物理放置的计算机程序。程序（a）基于从物理位置计算的延迟信息来识别关键节点。然后，程序（b）选择一组关键节点，并根据其布尔关系最佳地折叠其关键扇区和非关键扇区的一部分，其中至少包括一个关键节点。之后，程序（c）通过用最佳模式图覆盖其主题图来重新映射折叠的子网表，并动态地估计并更新扇出负载。如果重新映射的子网表不可接受，则程序返回到步骤（b），并且如果重新映射的子网表是可接受的，则在更新延迟信息和新映射的门的坐标之后返回到步骤（a）。步骤（a），当在步骤（a）中没有更多关键节点被识别时，该程序退出。

44. 发明授权

US06546539B1 Netlist resynthesis program using structure co-factoring 有权
标题翻译：网表再合成程序使用结构协同分解
公开(公告)号：US06546539B1
公开(公告)日：2003-04-08
申请号：US09736571
申请日：2000-12-14
申请人： Aiquo Lu , Ivan Pavisic , Pedja Raspopovic
发明人： Aiquo Lu , Ivan Pavisic , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A program for improving a netlist of logic nodes and physical placement for an IC. The program (A) identifies critical nodes based on time calculated from a physical placement. The program (B) selects a set of critical nodes and sub-netlists associated with the critical nodes and co-factors critical fan-ins in the sub-netlists. The program remaps the sub-netlists by optimization and dynamically estimates and updates fanout loads. The program returns to step B if the remapped sub-netlist is unacceptable, returns to step A if the remapped sub-netlist is acceptable, and exits at step A when no more critical nodes are identified at step A.
摘要翻译：用于改进IC的逻辑节点和物理放置的网表的程序。程序（A）基于从物理位置计算的时间来识别关键节点。程序（B）选择与关键节点相关联的一组关键节点和子网表，并在子网表中选择关联扇区的关键扇区。该程序通过优化重新映射子网表，并动态估计和更新扇出负载。如果重新映射的子网表不可接受，则程序返回到步骤B，如果重新映射的子网表可接受，则返回到步骤A，并且在步骤A没有在步骤A没有识别出更多的关键节点时退出步骤A.

45. 发明授权

US06487697B1 Distribution dependent clustering in buffer insertion of high fanout nets 有权
标题翻译：在高扇出网络的缓冲区插入中的分布依赖聚类
公开(公告)号：US06487697B1
公开(公告)日：2002-11-26
申请号：US09820059
申请日：2001-03-28
申请人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykh
发明人： Aiguo Lu , Ivan Pavisic , Andrej A. Zolotykh
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： Methods and apparatus are disclosed for inserting buffers into the design of an integrated circuit with a high fanout net. If a net has a ramptime violation, all of the driven elements in the net are clustered in such a manner that the total load (capacitance) of the driver decreases. Clustering is based upon a two-dimensional partitioning approach together with three proposed heuristics (expand, shrink and merge), which iteratively partitions the placement regions of the net such that the number of buffers to be inserted and the level of inserted buffer tree are minimized. After clustering, one buffer is inserted for each cluster created in the clustering operation. Each of the inserted buffers drives its corresponding cluster. The buffers that are inserted will not have any ramptime violation, which ensures converge of the buffer insertion scheme. Therefore, each insertion of a level of buffers reduces the overall ramptime of the net. After insertion of a level of buffers, the ramptime of the net is checked once again. If it is still not acceptable, the aforementioned clustering and insertion are repeated and the above cycle is iterated until there is no ramptime violation. During the first iteration of clustering and buffer insertion, the original circuit elements are clustered. After the first iteration of clustering and buffer insertion, the driven elements that are clustered are the buffers that were inserted in the previous iteration. In this manner, levels of buffers may be inserted into the net.
摘要翻译：公开了用于将缓冲器插入到具有高扇出网络的集成电路的设计中的方法和装置。如果一个网络具有呃违反时间，则网络中的所有被驱动元素都会以驱动器的总负载（电容）减小的方式聚集。聚类基于二维分割方法以及三个提出的启发式（扩展，收缩和合并），其迭代地分割网络的放置区域，使得要插入的缓冲器的数量和插入的缓冲器树的级别被最小化。聚类后，为在集群操作中创建的每个集群插入一个缓冲区。每个插入的缓冲区驱动其对应的集群。插入的缓冲区将不会有任何ramptime违规，这确保缓冲区插入方案的收敛。因此，每次插入一级缓冲区可以减少网络的总体上网时间。在插入一级缓冲区后，再次检查网络的启动时间。如果仍然不能接受，则重复前述的聚类和插入，并重复上述循环，直到没有突发性违反。在集群和缓冲区插入的第一次迭代期间，原始电路元件被聚集。在集群和缓冲区插入的第一次迭代之后，聚集的被驱动元素是在先前迭代中插入的缓冲区。以这种方式，可以将缓冲器的级别插入到网中。

46. 发明授权

US06186676B1 Method and apparatus for determining wire routing 失效
标题翻译：用于确定线路布线的方法和装置
公开(公告)号：US06186676B1
公开(公告)日：2001-02-13
申请号：US08906947
申请日：1997-08-06
申请人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
发明人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that wire routine be done correctly to avoid any congestion of wires. Congestion of wires can be determined by actually routing of the wires to connect the cells; however, the routing process is computationally expensive. For determination of congestion, the only required information are the location of the connections, or edges, to connect the pins of the IC. The present invention discloses a method to quickly provide a good estimate of the location of the edges, or connections for an IC. The present invention provides for a method to determine all the edges and superedges (bounding boxes, or areas where an edge will take space) of an IC without requiring to determine the actual routing of the wires of an IC.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。由于需要大量的单元和复杂的连接，因此必须正确地进行线路程序，以避免导线的拥塞。可以通过实际布线连接电池来确定电线的拥塞; 然而，路由过程在计算上是昂贵的。为了确定拥塞，唯一需要的信息是连接IC的引脚的连接或边缘的位置。本发明公开了一种快速提供对于IC的边缘或连接的位置的良好估计的方法。本发明提供了一种确定集成电路的所有边缘和覆盖（边界将占据空间的区域）的方法，而不需要确定IC的导线的实际布线。

47. 发明授权

US6123736A Method and apparatus for horizontal congestion removal 失效
标题翻译：水平堵塞消除的方法和装置
公开(公告)号：US6123736A
公开(公告)日：2000-09-26
申请号：US906949
申请日：1997-08-06
申请人： Ivan Pavisic , Ranko Scepanovic , Alexander E. Andreev
发明人： Ivan Pavisic , Ranko Scepanovic , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. Placement of the cells and the routing of the wires to avoid congestion can be accomplished by determining congestion of various regions, or pieces, of the IC's after an initial placement of the cells and routing of the wires. The present invention discloses a method and apparatus to define the regions, or pieces, of the IC, determine various density measurement of the pieces, and adjust the sizes of the pieces to reduce congestion of congested pieces by reallocating space from uncongested pieces to congested pieces. In addition, the present invention discloses the technique of adjusting the sizes of the piece to minimize disturbing the placement and wire routing while the congestion is being reduced. This is accomplished by comparing the vertical location of each of the pieces to the vertical location of the pieces next to it.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。由于需要大量的单元和复杂的连接，所以必须正确地进行单元和电线程序的布置，以避免导线堵塞。可以通过在单元的初始放置和导线的布线之后确定IC的各个区域或多个块的拥塞来实现单元的放置和布线以避免拥塞。本发明公开了一种用于限定IC的区域或片段的方法和装置，确定片段的各种密度测量，并调整片段的尺寸，以通过将空隙重新分配成未充塞的片段到拥塞的部分来减少拥塞片的拥塞。此外，本发明公开了一种在减少拥塞的情况下调整片的大小以最小化扰乱布局和布线的技术。这是通过将每个片段的垂直位置与其旁边的片段的垂直位置进行比较来实现的。

48. 发明授权

US5875118A Integrated circuit cell placement parallelization with minimal number of conflicts 失效
标题翻译：集成电路单元放置与最少数量的冲突并行化
公开(公告)号：US5875118A
公开(公告)日：1999-02-23
申请号：US798653
申请日：1997-02-11
申请人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for maximizing effectiveness of parallel processing, using multiple processors, to achieve an optimal cell placement layout on an integrated circuit (IC) chip is disclosed. The method requires the cells of the IC to be assigned to one of the multiple processors in a manner to balance the work load among the multiple processors. Then, the affinity of the cells to each of the multiple processors is determined. The affinity of the cells, including the conflict reduction factors and work load balancing factors, is used to reassign the cells to the processors. The cell affinity calculation and the processor reassignment are repeated until no cells are reassigned or for a fixed number of times. The assignment of the cells to the multiple processors and subsequent reassignments of the cells based on affinity of the cells to the processors reduces or eliminates the problems associated with prior parallel cell placement techniques.
摘要翻译：公开了一种用于最大化使用多个处理器的并行处理的有效性以在集成电路（IC）芯片上实现最佳单元布局布局的方法。该方法要求以多个处理器之间的工作负载平衡的方式将IC的单元分配给多个处理器之一。然后，确定小区对多个处理器中的每一个的亲和性。使用包括冲突减少因子和工作负载均衡因素在内的小区的亲和性将这些小区重新分配给处理器。重复细胞亲和度计算和处理器重新分配，直到没有细胞被重新分配或固定次数为止。基于小区对处理器的亲和性的将小区分配给多个处理器和随后的小区重新分配减少或消除与先前的并行小区布置技术相关的问题。

49. 发明申请

US20120278783A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 失效
标题翻译：信号延迟减少系统
公开(公告)号：US20120278783A1
公开(公告)日：2012-11-01
申请号：US13544632
申请日：2012-07-09
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.
摘要翻译：提供了一种减少信号偏移的系统和方法。该方法包括接收具有组件之间的组件和连接的网表。每个连接具有至少一个信号线。识别多个网络组，每个网络组包括至少一些连接并且期望等效路由。对于每个网络组，所述方法包括系统地路由用于连接的组件之间的连接路径，每个连接路径在组件之一的输出和至少一个其他组件的输入之间延伸并且包括至少一个路径片段。对于网络组的至少一个连接，路由包括在与连接路径的路径片段中的至少一个相邻并且平行的路由信道中路由至少一个接地屏蔽线。

50. 发明申请

US20080109688A1 Built in self test transport controller architecture 失效
标题翻译：内置自检传输控制器架构
公开(公告)号：US20080109688A1
公开(公告)日：2008-05-08
申请号：US11557513
申请日：2006-11-08
申请人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
发明人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/34 , G11C2029/0401 , G11C2029/1204 , G11C2029/2602
摘要： A built in self test circuit disposed within a memory matrix. Individual memory cells within the memory matrix are disposed into logical columns. The built in self test circuit has only one memory test controller, which is adapted to initiate test commands and receive test results. Transport controllers are uniquely paired with each one of the logical columns of memory cells. Each of the transport controllers is adapted to receive test commands from the memory test controller, test memory cells within the logical column as instructed by the test commands, receive test results from the logical column of memory cells, and provide the test results to the memory test controller. The transport controllers are also adapted to selectively operate in three different modes under control of the memory test controller. A first production testing mode simultaneously tests the memory cells in different logical columns, while accumulating the test results for a given logical column with the transport controller associated with the given logical column. A second production testing mode retrieves the accumulated test results from the transport controllers. A diagnostic testing mode tests memory cells within one selected logical column, while simultaneously retrieving the test results for the one selected logical column.
摘要翻译：设置在存储器矩阵内的内置自测电路。存储器矩阵内的单个存储单元被放置在逻辑列中。内置自检电路只有一个内存测试控制器，适用于启动测试命令并接收测试结果。传输控制器与每个存储单元的逻辑列唯一配对。每个传输控制器适于从存储器测试控制器接收测试命令，根据测试命令指示在逻辑列中测试存储器单元，从存储器单元的逻辑列接收测试结果，并将测试结果提供给存储器测试控制器传输控制器还适于在存储器测试控制器的控制下以三种不同的模式选择性地操作。第一个生产测试模式同时测试不同逻辑列中的存储单元，同时使用与给定逻辑列相关联的传输控制器累积给定逻辑列的测试结果。第二个生产测试模式从运输控制器检索累积的测试结果。诊断测试模式测试一个所选逻辑列内的存储单元，同时检索所选逻辑列的测试结果。

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