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41. 发明授权

US06600345B1 Glitch free clock select switch 有权
标题翻译：无毛刺时钟选择开关
公开(公告)号：US06600345B1
公开(公告)日：2003-07-29
申请号：US10002921
申请日：2001-11-15
申请人： Frederic Boutaud
发明人： Frederic Boutaud
IPC分类号： H03K1700
CPC分类号： G06F1/08 , H03K5/1252 , H04L7/0083
摘要： A clock selection circuit for selecting one of a plurality of clocks as an output clock. When the selection circuit switches between two of the plurality of clocks for output, the currently output clock is removed from the output. The removal of the currently output clock is performed synchronously to the currently selected clock. The newly selected clock is then coupled to the output. Coupling of the newly selected clock is performed synchronously to the newly selected clock.
摘要翻译：一种用于选择多个时钟之一作为输出时钟的时钟选择电路。当选择电路在多个时钟中的两个之间切换以输出时，从输出中去除当前输出的时钟。与当前选择的时钟同步地执行当前输出时钟的去除。新选择的时钟然后耦合到输出。新选择的时钟的耦合与新选择的时钟同步地执行。

42. 发明授权

US06334181B1 DSP with wait state registers having at least two portions 失效
标题翻译：具有等待状态寄存器的DSP具有至少两个部分
公开(公告)号：US06334181B1
公开(公告)日：2001-12-25
申请号：US09360488
申请日：1999-07-23
申请人： Frederic Boutaud , Peter N. Ehlig
发明人： Frederic Boutaud , Peter N. Ehlig
IPC分类号： G06F1500
CPC分类号： G01R31/318536 , G01R31/318505 , G06F9/30 , G06F9/30058 , G06F9/30072 , G06F9/30094 , G06F9/325 , G06F11/2733 , G06F11/3648 , G06F11/3652
摘要： A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.
摘要翻译：数据处理设备与具有接收者和不同通信响应周期的外围设备一起使用。数据处理装置包括数字处理器，其适于通过断言每个所选择的外围设备的地址来选择不同的外围设备。可寻址可编程寄存器保持等待状态值，表示与不同地址范围对应的不同等待状态数。响应于由数字处理器断言的外围设备的断言地址的电路产生由保持在可寻址可编程寄存器之一中的值所表示的等待状态数量，该可寻址的可编程寄存器对应于其中发出有效地址的地址范围中的一个，从而容纳外围设备的通信响应周期不同。

43. 发明授权

US06249860B1 System with wait state registers 失效
公开(公告)号：US06249860B1
公开(公告)日：2001-06-19
申请号：US09431505
申请日：1999-11-01
申请人： Frederic Boutaud , Peter N. Ehlig
发明人： Frederic Boutaud , Peter N. Ehlig
IPC分类号： G06F1500
CPC分类号： G01R31/318536 , G01R31/318505 , G06F9/30 , G06F9/30058 , G06F9/30072 , G06F9/30094 , G06F9/325 , G06F11/2733 , G06F11/3648 , G06F11/3652
摘要： A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

44. 发明授权

US06247111B1 System with wait state register 失效
标题翻译：具有等待状态寄存器的系统
公开(公告)号：US06247111B1
公开(公告)日：2001-06-12
申请号：US09430960
申请日：1999-11-01
申请人： Frederic Boutaud , Peter N. Ehlig
发明人： Frederic Boutaud , Peter N. Ehlig
IPC分类号： G06F1500
CPC分类号： G01R31/318536 , G01R31/318505 , G06F9/30 , G06F9/30058 , G06F9/30072 , G06F9/30094 , G06F9/325 , G06F11/2733 , G06F11/3648 , G06F11/3652
摘要： A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.
摘要翻译：数据处理设备与具有接收者和不同通信响应周期的外围设备一起使用。数据处理装置包括数字处理器，其适于通过断言每个所选择的外围设备的地址来选择不同的外围设备。可寻址可编程寄存器保持等待状态值，表示与不同地址范围对应的不同等待状态数。响应于由数字处理器断言的外围设备的断言地址的电路产生由保持在可寻址可编程寄存器之一中的值所表示的等待状态数量，该可寻址的可编程寄存器对应于其中发出有效地址的地址范围中的一个，从而容纳外围设备的通信响应周期不同。

45. 发明授权

US5787481A System for managing write and/or read access priorities between central processor and memory operationally connected 失效
标题翻译：用于管理中央处理器和存储器之间的写入和/或读取访问优先级的系统，用于操作连接
公开(公告)号：US5787481A
公开(公告)日：1998-07-28
申请号：US847550
申请日：1997-04-23
申请人： Frederic Boutaud , Sigheshi Abiko
发明人： Frederic Boutaud , Sigheshi Abiko
IPC分类号： G06F12/00 , G06F9/38 , G06F13/26 , G06F13/00
CPC分类号： G06F9/3834 , G06F9/3824
摘要： A system for managing write and/or read access priorities between a central processing unit (CPU) and at least one memory (11) which includes mechanism for managing invalid accesses to the memory, The system comprises: an address comparator (19) able to test at each time instant the equality of the write and read addresses in memory, and in the event of equality of the addresses, to generate a signal (35) representative of a condition of invalid access to the memory. A diversion multiplexer circuit (27) is controlled by the invalid access signal (35), in such a way as to connect the bus (33) for reading to the CPU, either to the memory data read bus (31;31') in the event of the absence of an invalid access, or to the bus (29;29') for writing data from the CPU to the memory in the event of invalid access signal being present, so that the memory data write bus is diverted to the read bus by the CPU in the event of an attempted invalid access of the memory by the CPU.
摘要翻译：一种用于在中央处理单元（CPU）和至少一个存储器（11）之间管理写入和/或读取访问优先级的系统，其包括用于管理对存储器的无效访问的机制。该系统包括：地址比较器（19），其能够在每个时刻瞬间测试存储器中写入和读取地址的相等性，并且在地址相等的情况下，生成代表对存储器的无效访问条件的信号（35）。分流多路复用器电路（27）由无效接入信号（35）控制，以便将用于读取的总线（33）连接到CPU，或者与存储器数据读总线（31; 31'）没有无效访问的事件，或者在存在无效访问信号的情况下从CPU向存储器写入数据的总线（29; 29'），使得存储器数据写总线被转移到在CPU尝试无效访问存储器的情况下，CPU读取总线。

46. 发明授权

US5579497A Devices and systems with parallel logic unit, and methods 失效
标题翻译：具有并行逻辑单元的设备和系统以及方法
公开(公告)号：US5579497A
公开(公告)日：1996-11-26
申请号：US484115
申请日：1995-06-07
申请人： Peter N. Ehlig , Frederic Boutaud
发明人： Peter N. Ehlig , Frederic Boutaud
IPC分类号： G01R31/3185 , G06F7/544 , G06F9/30 , G06F9/302 , G06F9/46 , G06F11/267 , G06F11/36 , G06F19/00
CPC分类号： G01R31/318536 , G06F11/2236 , G06F11/3652 , G06F7/544 , G06F9/30014 , G06F9/30021 , G06F9/462
摘要： A data processing device includes a data bus and a program bus, a data memory connected to the data bus and having data memory locations, and an electronic computation unit connected to the data bus and an accumulator connected to the electronic computation unit and to the data bus. A logic circuit is connected to the program bus for receiving instructions and connected to the data bus for executing logic operations in accordance with at least some of the instructions. The logic operations affect bits in at least one of the data memory locations independently of the electronic computation unit without affecting the accumulator. A control circuit sends instructions to the logic circuit on the program bus and to the electronic computation unit. Other devices, systems and methods are also disclosed.
摘要翻译：数据处理装置包括数据总线和程序总线，连接到数据总线并具有数据存储器位置的数据存储器，以及连接到数据总线的电子计算单元和连接到电子计算单元和数据的累加器总线。逻辑电路连接到程序总线，用于接收指令并连接到数据总线，用于根据至少一些指令执行逻辑操作。逻辑运算影响独立于电子计算单元的至少一个数据存储单元中的位而不影响累加器。控制电路向程序总线上的逻辑电路和电子计算单元发送指令。还公开了其他装置，系统和方法。

47. 发明授权

US5579218A Devices and systems with parallel logic unit, and methods 失效
公开(公告)号：US5579218A
公开(公告)日：1996-11-26
申请号：US485205
申请日：1995-06-07
申请人： Peter N. Ehlig , Frederic Boutaud
发明人： Peter N. Ehlig , Frederic Boutaud
IPC分类号： G01R31/3185 , G06F7/544 , G06F9/30 , G06F9/302 , G06F9/46 , G06F11/267 , G06F11/36 , G06F19/00
CPC分类号： G01R31/318536 , G06F11/2236 , G06F11/3652 , G06F7/544 , G06F9/30014 , G06F9/30021 , G06F9/462
摘要： A data processing device includes a data bus and a program bus, a data memory connected to the data bus and having data memory locations, and an electronic computation unit connected to the data bus and an accumulator connected to the electronic computation unit and to the data bus. A logic circuit is connected to the program bus for receiving instructions and connected to the data bus for executing logic operations in accordance with at least some of the instructions. The logic operations affect bits in at least one of the data memory locations independently of the electronic computation unit without affecting the accumulator. A control circuit sends instructions to the logic circuit on the program bus and to the electronic computation unit. Other devices, systems and methods are also disclosed.

48. 发明授权

US5072418A Series maxium/minimum function computing devices, systems and methods 失效
标题翻译：系列最大/最小功能计算设备，系统和方法
公开(公告)号：US5072418A
公开(公告)日：1991-12-10
申请号：US347596
申请日：1989-05-04
申请人： Frederic Boutaud , Peter N. Ehlig
发明人： Frederic Boutaud , Peter N. Ehlig
IPC分类号： G01R31/3185 , G06F7/544 , G06F9/30 , G06F9/302 , G06F9/46 , G06F11/267 , G06F11/36
CPC分类号： G01R31/318536 , G06F11/2236 , G06F11/3652 , G06F7/544 , G06F9/30014 , G06F9/30021 , G06F9/462
摘要： A data processing device includes an instruction decoder and an arithmetic logic unit having first and second inputs and an output. An accumulator is connected between the output and first input of the arithmetic logic unit. A further register is connected between the accumulator and the second input of the arithmetic logic unit. The arithmetic logic unit includes circuitry for computing a digital value to the accumulator as well as an additional circuit. The additional circuit thereupon compares the value at the second input from said register with the digital value in the accumulator in response to a command from the instruction decoder and then stores to the register the lesser or the greater in value of the contents of the register and the digital value in the accumulator depending on the command. Other devices, systems and methods are also disclosed.
摘要翻译：数据处理装置包括指令解码器和具有第一和第二输入和输出的算术逻辑单元。累加器连接在算术逻辑单元的输出和第一输入端之间。累加器和算术逻辑单元的第二输入端之间连接一个寄存器。算术逻辑单元包括用于计算累加器的数字值以及附加电路的电路。附加电路响应于来自指令解码器的命令将来自所述寄存器的第二输入处的值与累加器中的数字值进行比较，然后向寄存器存储寄存器的内容的较小值或更大值，累加器中的数字值取决于命令。还公开了其他装置，系统和方法。

49. 发明授权

US5072219A Digital-analog conversion system including a digital modulator having several quantification levels, associated with a digital-analog converter 失效
标题翻译：数字模拟转换系统，包括具有与数字模拟转换器相关的几个数量级的数字调制器
公开(公告)号：US5072219A
公开(公告)日：1991-12-10
申请号：US476088
申请日：1990-02-07
申请人： Frederic Boutaud , Pierre Carbou , Paul Correia
发明人： Frederic Boutaud , Pierre Carbou , Paul Correia
IPC分类号： H03H19/00 , H03M1/74 , H03M3/02 , H03M7/00
CPC分类号： H03M7/3026 , H03M3/502 , H03M7/3042
摘要： This digital-analog conversion system comprises a digital modulator (1) having several quantification levels formed by a second order Delta-Sigma modulator and a digital-analog converter and switched capacitors filter set (3) whose law of progression between the different analog levels is independent of the absolute and relative values of the constituent components of the said assembly.
摘要翻译：该数字 - 模拟转换系统包括数字调制器（1），其具有由二阶Δ-Σ调制器和数模转换器和开关电容器滤波器组（3）形成的若干定量电平，其中不同模拟电平之间的进行规律为独立于所述组件的构成部件的绝对值和相对值。

50. 发明授权

US4827249A Video system with combined text and graphics frame memory 失效
标题翻译：具有组合文字和图形帧存储器的视频系统
公开(公告)号：US4827249A
公开(公告)日：1989-05-02
申请号：US082965
申请日：1987-08-05
申请人： Gerard Chauvel , Frederic Boutaud
发明人： Gerard Chauvel , Frederic Boutaud
IPC分类号： G09G1/02 , G09G1/06 , G09G1/16 , G09G1/28 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/30 , G09G5/36 , G09G5/39 , G09G5/42
CPC分类号： G09G5/022 , G09G5/42
摘要： This system includes a composite memory (5) in which are memorized the data for images to be displayed for each frame. A video display processor (12) controls the screen (8). A central processing unit (1) effects the composition of the image with the memory and an address processor (10), the extraction of the point data to be displayed being effected by a time base circuit (BT) synchronized with the sweeping of the screen, and by a control device (15) for dynamic access which distributes the access times among different units utilizing the memory. The memory (5) includes a first control memory for the memorization of a data word for a line or group of lines making up the image, each word having an address value for addressing a second control memory which contains, at each of these addresses, at least one display attribute data word characterizing the contents of the line(s) corresponding to the value of the respective address of the first control memory. A zone memory is provided for storing, in addressable zones, the text or graphics information for those lines which have intelligible information. For each of the lines having such information, a data word following the display attribute data word contains the initial address in the zone memory of the corresponding zone which contains the intelligible information to be displayed on the line.
摘要翻译：该系统包括复合存储器（5），其中存储要针对每帧显示的图像的数据。视频显示处理器（12）控制屏幕（8）。中央处理单元（1）利用存储器和地址处理器（10）实现图像的组成，通过与屏幕扫描同步的时基电路（BT）来实现要显示的点数据的提取，以及用于利用存储器在不同单元之间分配访问时间的用于动态访问的控制设备（15）。存储器（5）包括用于存储构成图像的一行或一组线的数据字的第一控制存储器，每个字具有用于寻址第二控制存储器的地址值，该第二控制存储器在每个这些地址处包含至少一个显示属性数据字表征对应于第一控制存储器的相应地址的值的行的内容。提供区域存储器用于在可寻址区域中存储具有可理解信息的那些线路的文本或图形信息。对于具有这种信息的每一行，显示属性数据字之后的数据字包含相应区域的区域存储器中的初始地址，其中包含要在该行上显示的可理解信息。

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