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41. 发明申请

US20090063828A1 Systems and Methods for Communication between a PC Application and the DSP in a HDA Audio Codec 审中-公开
标题翻译： PC应用程序与HDA音频编解码器中的DSP之间的通信系统和方法
公开(公告)号：US20090063828A1
公开(公告)日：2009-03-05
申请号：US12202356
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
发明人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
IPC分类号： G06F9/315
CPC分类号： G06F3/162
摘要： Systems and methods implemented in a PC for enabling communication between an application executing on the CPU and a DSP that is incorporated into a codec in the High Definition Audio (HDA) system, wherein the communication is carried out via the HDA bus. In one embodiment, an HDA codec includes one or more conventional HDA widgets coupled to a programmable processor such as a DSP. The codec includes a set of registers that are configured to store HDA verbs and data transmitted via the HDA bus. The programmable processor is configured to identify verbs that indicate associated information is a communication from an application executing on the CPU, read the associated information, and process the information according to the associated verbs. The information may be program instructions, parametric data, requests for information, etc.
摘要翻译：在PC中实现的用于实现在CPU上执行的应用程序与被并入高清晰度音频（HDA）系统中的编解码器的DSP之间的通信的系统和方法，其中通过HDA总线进行通信。在一个实施例中，HDA编解码器包括耦合到诸如DSP的可编程处理器的一个或多个常规HDA小部件。编解码器包括一组寄存器，用于存储通过HDA总线传输的HDA动词和数据。可编程处理器被配置为识别指示相关信息的动词是来自在CPU上执行的应用程序的通信，读取相关联的信息，以及根据相关联的动词处理信息。该信息可以是程序指令，参数数据，信息请求等。

42. 发明申请

US20090063738A1 Systems and Methods for Overriding Hardwired Responses in an HDA Codec 失效
标题翻译：用于覆盖HDA编解码器中的硬连线响应的系统和方法
公开(公告)号：US20090063738A1
公开(公告)日：2009-03-05
申请号：US12202358
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas
发明人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas
IPC分类号： G06F13/42
CPC分类号： G06F3/162
摘要： Systems and methods for overriding hardwired responses of a codec to High Definition Audio (HDA) verbs that are received from an HDA controller. In one embodiment, an HDA codec is configured to store one or more overriding responses, each of which is associated with a corresponding HDA verb. When an HDA verb is received by the codec, the codec determines whether the verb is associated with one of the overriding responses. If the verb is associated with one of the overriding responses, the overriding response is returned to the HDA controller. If the first HDA verb is not associated with one of the stored overriding responses, provide a hardwired response associated with the first HDA verb to the HDA bus. Overriding responses can be returned for unsupported verbs only, or for any verbs that prompt responses.
摘要翻译：用于将编解码器的硬连线响应覆盖从HDA控制器接收的高清晰度音频（HDA）动词的系统和方法。在一个实施例中，HDA编解码器被配置为存储一个或多个覆盖的响应，每一个响应与相应的HDA动词相关联。当编解码器接收到HDA动词时，编解码器确定动词是否与其中一个重写的响应相关联。如果动词与其中一个覆盖的响应相关联，则覆盖的响应将返回给HDA控制器。如果第一HDA动词与存储的覆盖应答之一不相关联，则向HDA总线提供与第一HDA动词相关联的硬连线响应。可以仅针对不支持的动词或任何提示响应的动词返回重写响应。

43. 发明申请

US20090062948A1 Systems and Methods for Controlling Audio Volume in the Processor of a High Definition Audio Codec 失效
标题翻译：用于控制高分辨率音频编解码器处理器中音频音量的系统和方法
公开(公告)号：US20090062948A1
公开(公告)日：2009-03-05
申请号：US12202355
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
发明人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
IPC分类号： G06F17/00
CPC分类号： H03G3/3089 , G06F3/16 , G10L15/26 , G11B20/10527 , G11B2020/10574 , H03F3/217
摘要： Systems and methods for controlling the audio volume of an audio signal in an HDA codec having a programmable processor such as a DSP, wherein the codec receives digital audio signals and audio volume control verbs over an HDA bus, and the audio volume levels associated with the audio volume control verbs are used by the processor in the generation pulse width modulated (PWM) output signals, thereby controlling the audio volume levels of the output signals. The processor may be configured to adjust non-volume parameters such as PWM deadtime, in addition to adjusting audio volume, based on the audio volume levels. The codec may be implemented in a PC or other system that implements an HDA system that includes the HDA bus and HDA codec.
摘要翻译：用于控制具有诸如DSP的可编程处理器的HDA编解码器中的音频信号的音频音量的系统和方法，其中编解码器通过HDA总线接收数字音频信号和音频音量控制动词，以及与音频音量控制动词由处理器在生成脉宽调制（PWM）输出信号中使用，从而控制输出信号的音频音量。除了根据音频音量水平调整音频音量之外，处理器可以被配置为调整诸如PWM死时间之类的非体积参数。编解码器可以在实现包括HDA总线和HDA编解码器的HDA系统的PC或其他系统中实现。

44. 发明申请

US20090060228A1 Systems and Methods for Shadowing an HDA Codec 失效
标题翻译：用于影像HDA编解码器的系统和方法
公开(公告)号：US20090060228A1
公开(公告)日：2009-03-05
申请号：US12202360
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas , Adam Zaharias
发明人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas , Adam Zaharias
IPC分类号： H03F21/00 , G06F3/00
CPC分类号： G06F3/162
摘要： Systems and methods for “shadowing” a target codec to provide additional features that are not available in the target codec. In one embodiment, an audio amplification system includes a High Definition Audio (HDA) bus, and an HDA controller, a conventional HDA codec and a shadow HDA codec coupled to the HDA bus. The conventional codec receives audio data and commands from the HDA controller via the bus and processes them to generate an output audio signal. The shadow codec snoops the audio data and commands on the HDA bus that are targeted to the conventional codec. The shadow codec processes the snooped audio data and commands to generate a second audio output. The shadow codec does not communicate with the HDA controller and is transparent to the controller. The shadow codec does not request enumeration from the HDA controller and does not receive an address from the HDA controller.
摘要翻译：用于“遮蔽”目标编解码器以提供目标编解码器中不可用的附加功能的系统和方法。在一个实施例中，音频放大系统包括高清晰度音频（HDA）总线和HDA控制器，传统的HDA编解码器和耦合到HDA总线的影子HDA编解码器。常规编解码器经由总线从HDA控制器接收音频数据和命令，并处理它们以产生输出音频信号。影子编解码器侦听HDA总线上的传统编解码器的音频数据和命令。影子编解码器处理窥探的音频数据和命令以产生第二个音频输出。影子编解码器不与HDA控制器通信，对控制器是透明的。影子编解码器不要求来自HDA控制器的枚举，也不会从HDA控制器接收地址。

45. 发明授权

US06499086B2 Processor with decompressed video bus 有权
标题翻译：具有解压缩视频总线的处理器
公开(公告)号：US06499086B2
公开(公告)日：2002-12-24
申请号：US09770461
申请日：2001-01-29
申请人： Steven L. Belt , Douglas D. Gephardt , Drew J. Dutton , Brett B. Stewart , Rita M. Wisor
发明人： Steven L. Belt , Douglas D. Gephardt , Drew J. Dutton , Brett B. Stewart , Rita M. Wisor
IPC分类号： G06F1200
CPC分类号： G06F12/0875
摘要： A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.
摘要翻译：在中央处理单元和周边单元之间的专用总线，例如驱动视频显示器的图形控制器，在中央处理单元内发生信号处理的环境中提供增强的能力。专用总线减轻了诸如PCI总线的其他数据总线，需要传送大量数据，例如解压缩的视频数据。所得到的系统支持解压缩视频数据的高带宽传输，实现高分辨率24位全动态视频和多数据流视频。

46. 发明授权

US5901332A System for dynamically reconfiguring subbusses of data bus according to system needs based on monitoring each of the information channels that make up data bus 失效
标题翻译：根据系统需要动态重新配置数据总线子系统的系统，基于监控构成数据总线的每个信息通道
公开(公告)号：US5901332A
公开(公告)日：1999-05-04
申请号：US921078
申请日：1997-08-29
申请人： Douglas D. Gephardt , Brett B. Stewart , Rita M. Wisor , Steven L. Belt , Drew J. Dutton
发明人： Douglas D. Gephardt , Brett B. Stewart , Rita M. Wisor , Steven L. Belt , Drew J. Dutton
IPC分类号： G06F13/38 , G06F13/40
CPC分类号： G06F13/4018 , G06F13/385
摘要： A data bus for connecting information processing devices is configurable into a plurality of subbusses in order to fully utilize the data bus capacity. The size and data transfer direction of each subbus, as well as the data transfer speed of each subbus, is independent of the other subbusses. Also, the data bus can be reconfigured to meet changing system requirements. A data bus controller is thus provided to accomplish this data bus reconfiguration. The reconfiguration may be accomplished in accordance with one of a plurality of information flow templates which may be stored in a memory. A method of configuring a data bus is also provided wherein information transfer needs of a system are identified and the data bus is configured according to the identified information transfer means. The reconfiguration in accordance with the information transfer needs may be accomplished in accordance with one or more information flow templates which may be stored in a memory. The system may operate in accordance with a self arbitration scheme such that reconfiguration of the system is based on operational experience, such as utilization rates or excess capacity associated with each of the subbusses.
摘要翻译：用于连接信息处理设备的数据总线可配置成多个子总线，以便充分利用数据总线容量。每个子总线的大小和数据传输方向以及每个子总线的数据传输速度与其他子总线无关。此外，数据总线可以重新配置以满足不断变化的系统要求。因此提供数据总线控制器来完成该数据总线重新配置。重新配置可以根据可存储在存储器中的多个信息流模板之一来完成。还提供了一种配置数据总线的方法，其中识别系统的信息传送需求，并且根据所识别的信息传送装置配置数据总线。根据信息传送需求的重新配置可以根据可存储在存储器中的一个或多个信息流模板来完成。系统可以根据自我仲裁方案操作，使得系统的重新配置基于诸如与每个子总线相关联的利用率或过多容量的操作经验。

47. 发明授权

US5734843A Reverse data channel as a bandwidth modulator 失效
标题翻译：反向数据通道作为带宽调制器
公开(公告)号：US5734843A
公开(公告)日：1998-03-31
申请号：US476872
申请日：1995-06-07
申请人： Douglas D. Gephardt , Brett B. Stewart , Rita M. Wisor , Drew J. Dutton , Steven L. Belt
发明人： Douglas D. Gephardt , Brett B. Stewart , Rita M. Wisor , Drew J. Dutton , Steven L. Belt
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/36
摘要： A method of allocating bandwidth among a plurality of devices communicatively connected through a data bus provides for determining a data need of at least one of the plurality of devices, allocating portions of the data bus to the devices in response to the data need, and transmitting data between the devices on the allocated portions of the data bus. The portions of the data bus can be subbusses, each comprising at least one bit line. The data need can be based on a measure of fullness of a buffer corresponding to the at least one device. The data need can be provided as feedback from the buffer to a data bus controller which allocates the portions of the data bus. The method can use rules for assigning the subbusses which are stored in a memory. A processor can change the rules to accommodate changing conditions in the data bus. Also provided is a data communication system comprising a dynamically reconfigurable data bus, a data bus controller connected to the dynamically reconfigurable data bus for configuring subbusses of the data bus, a plurality of receiving devices connected to the data bus, and a feedback connection from at least one of the receiving devices to the data bus controller, wherein the data bus controller configures the subbusses in accordance with feedback received over the feedback connection. A memory can be connected to the data bus controller for storing rules for use by the data bus controller in configuring the subbusses. A processor can change the rules to accommodate changing conditions in the data bus.
摘要翻译：在通过数据总线通信连接的多个设备之间分配带宽的方法提供用于确定多个设备中的至少一个设备的数据需求，响应于数据需要将数据总线的部分分配给设备，并且发送在数据总线的分配部分上的设备之间的数据。数据总线的部分可以是子总线，每个都包括至少一个位线。数据需要可以基于对应于至少一个设备的缓冲器的丰满度的量度。数据需求可以作为从缓冲器到分配数据总线部分的数据总线控制器的反馈来提供。该方法可以使用用于分配存储在存储器中的子总线的规则。处理器可以改变规则以适应数据总线中的变化条件。还提供了一种数据通信系统，包括动态可重新配置的数据总线，连接到动态可重配置数据总线的数据总线控制器，用于配置数据总线的子总线，连接到数据总线的多个接收设备，以及来自至少一个接收设备到达数据总线控制器，其中数据总线控制器根据通过反馈连接接收到的反馈来配置子总线。存储器可以连接到数据总线控制器，用于存储数据总线控制器在配置子总线时使用的规则。处理器可以改变规则以适应数据总线中的变化条件。

48. 发明授权

US5632020A System for docking a portable computer to a host computer without suspending processor operation by a docking agent driving the bus inactive during docking 失效
标题翻译：用于将便携式计算机对接到主计算机的系统，而不会在对接代理中暂停处理器操作，从而驱动总线在停靠期间无效
公开(公告)号：US5632020A
公开(公告)日：1997-05-20
申请号：US255663
申请日：1994-06-09
申请人： Douglas D. Gephardt , Scott Swanstrom
发明人： Douglas D. Gephardt , Scott Swanstrom
IPC分类号： G06F3/00 , G06F1/16 , G06F13/14 , G06F13/362 , G06F13/364 , G06F13/38 , G06F13/40 , G06F13/20 , G06F13/36
CPC分类号： G06F13/4081 , G06F1/1632 , G06F13/364 , G06F13/4031
摘要： A computer system includes a bus arbiter for providing immediate access to a bus in response to an external requirement or event. In a dockable computer system capable of hot docking or warm docking, the bus arbiter grants exclusive, non-preemptive access to the buses to the docking agent which is capable of quieting (rendering inactive) the bus of the portable computer and docking station in response to a notice signal. The notice signal is indicative of a change of states from the undocked state to the docked state or from the docked state to the undocked state. The notice signal may be provided from software, a user-actuated switch, or an infrared signal. In an audio-capable computer, the bus arbiter provides exclusive non-preemptive access to the digital signal processing peripheral device so that audio glitches are avoided. The arbiter preferably includes an override circuit for countermanding the fairness scheme employed by the bus arbiter and granting immediate bus access in response to the external event or condition. The bus arbiter preferably is able to provide fixed or rotating priority for bus accesses of other peripheral devices on the bus. The arbiter is preferably integrated with the main processor of the computer system.
摘要翻译：计算机系统包括总线仲裁器，用于响应于外部要求或事件提供对总线的即时访问。在能够进行热对接或热对接的可停靠的计算机系统中，总线仲裁器向对接代理授予对总线的独占的非抢占性访问，该对接代理能够响应于便携式计算机和对接站的总线（呈现无效）到一个通知信号。通知信号表示状态从脱离状态到对接状态或从对接状态到解除停止状态的变化。通知信号可以由软件，用户驱动的开关或红外信号提供。在音频计算机中，总线仲裁器提供对数字信号处理外围设备的独占非抢占式访问，从而避免了音频毛刺。仲裁器优选地包括用于对抗总线仲裁器采用的公平方案并且响应于外部事件或状况授权立即总线访问的超控电路。总线仲裁器优选地能够为总线上的其他外围设备的总线访问提供固定或旋转优先级。仲裁器最好与计算机系统的主处理器集成。

49. 发明授权

US5615207A Side bus to dynamically off load main bus 失效
标题翻译：侧总线动态卸载主总线
公开(公告)号：US5615207A
公开(公告)日：1997-03-25
申请号：US482045
申请日：1995-06-07
申请人： Douglas D. Gephardt , Brett B. Stewart , Rita M. Wisor , Drew J. Dutton , Steven L. Belt
发明人： Douglas D. Gephardt , Brett B. Stewart , Rita M. Wisor , Drew J. Dutton , Steven L. Belt
IPC分类号： H04L12/46
CPC分类号： H04L12/4616
摘要： A data communication system includes an express bus, a plurality of local buses, and a plurality of local/express bridges, each local/express bridge connecting a corresponding local bus to the express bus. A plurality of local/local bridges each connect two corresponding local buses. The plurality of local buses and the plurality of local/local bridges comprise a local path. Also provided is a method of communicating information from a sending communication device to a target communication device, comprising the steps of a) determining if the target communication device is on a local bus corresponding to the sending communication device, b) transferring the information from the sending communication device to the target communication device on the local bus corresponding to the sending communication device if the result of step a) is that the target communication device is on the local bus corresponding to the sending communication device, c) transferring the information from the sending communication device to an express bus if the result of step a) is that the target communication device is not on the local bus corresponding to the sending communication device, d) transferring the information from the express bus to a local bus corresponding to the target communication device, and e) transferring the information from the local bus corresponding to the target communication device to the target communication device.
摘要翻译：数据通信系统包括快速总线，多个本地总线和多个本地/快速桥接器，每个本地/快速桥接器将相应的本地总线连接到快速总线。多个本地/本地桥接器每个连接两个相应的本地总线。多个本地总线和多个本地/本地桥接器包括本地路径。还提供了一种从发送通信设备向目标通信设备传送信息的方法，包括以下步骤：a）确定目标通信设备是否在与发送通信设备相对应的本地总线上，b）将信息从如果步骤a）的结果是目标通信设备在与发送通信设备相对应的本地总线上，则将通信设备发送到与发送通信设备相对应的本地总线上的目标通信设备，c）将信息从如果步骤a）的结果是目标通信设备不在与发送通信设备相对应的本地总线上，则将通信设备发送到快速总线，d）将信息从快速总线传送到与目标对应的本地总线通信设备，以及e）从与ta相对应的本地总线传送信息 rget通信设备到目标通信设备。

50. 发明授权

US5218681A Apparatus for controlling access to a data bus 失效
标题翻译：用于控制访问数据总线的设备
公开(公告)号：US5218681A
公开(公告)日：1993-06-08
申请号：US576061
申请日：1990-08-31
申请人： Douglas D. Gephardt , James R. MacDonald
发明人： Douglas D. Gephardt , James R. MacDonald
IPC分类号： G06F13/36 , G06F13/14 , G06F13/40
CPC分类号： G06F13/4027 , G06F13/14
摘要： An apparatus for use with a host computing system for controlling access to a first data bus which is external of the host computing system and which first data bus is operatively connected with a second data bus internal of the host computing system. The apparatus comprises a local processing unit which is configured substantially the same as the host processing unit and is driven by a separate local program distinct from the host processing program driving the host processing unit. The apparatus further comprises a supplemental processing circuit for processing information, which supplemental processing circuit is responsive to the host processing unit and to the local processing unit to determine whether the host processing unit or the local processing unit has operative access to the first data bus. In its preferred embodiment, the first data bus and the second data bus are operatively connected by a configurable buffer circuit for effecting data bus connection. Further, in the preferred embodiment of the present invention, the supplemental processing circuit generates an intervention signal in response to the local processing unit, the buffer circuit responding to the intervention signal by configuring appropriately to provide operative access by the apparatus of the second data bus.

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