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41. 发明授权

US08030112B2 Method for fabricating MEMS device 有权
标题翻译：制造MEMS器件的方法
公开(公告)号：US08030112B2
公开(公告)日：2011-10-04
申请号：US12691754
申请日：2010-01-22
申请人： Tsung-Min Hsieh , Chien-Hsing Lee , Jhyy-Cheng Liou
发明人： Tsung-Min Hsieh , Chien-Hsing Lee , Jhyy-Cheng Liou
IPC分类号： H01L21/00
CPC分类号： B81C1/00246 , B81B2203/0315 , B81B2207/015 , B81C2201/016 , B81C2203/0714 , H04R19/005 , H04R19/04 , H04R31/00
摘要： A method for fabricating MEMS device includes: providing a single crystal substrate, having first surface and second surface and having a MEMS region and an IC region; forming SCS mass blocks on the first surface in the MEMS region; forming a structural dielectric layer over the first surface of the substrate, wherein a dielectric member of the structural dielectric layer is filled in spaces surrounding the SCS mass blocks in the MEMS region, the IC region has a circuit structure with an interconnection structure formed in the structural dielectric layer; patterning the single crystal substrate by an etching process on the second surface to expose a portion of the dielectric member filled in the spaces surrounding the SCS mass blocks; performing isotropic etching process at least on the dielectric portion filled in the spaces surrounding the SCS mass blocks. The SCS mass blocks are exposed to release a MEMS structure.
摘要翻译：一种制造MEMS器件的方法包括：提供具有第一表面和第二表面并具有MEMS区域和IC区域的单晶衬底; 在MEMS区域的第一表面上形成SCS质量块; 在所述基板的所述第一表面上形成结构介电层，其中所述结构介电层的电介质部件填充在所述MEMS区域中围绕所述SCS质量块的空间中，所述IC区域具有形成在所述MEMS区域中的互连结构的电路结构结构介电层; 通过在第二表面上的蚀刻工艺对单晶衬底进行图案化，以暴露填充在围绕SCS质量块的空间中的电介质构件的一部分; 至少在填充在SCS质量块周围的空间中的电介质部分上进行各向同性蚀刻处理。暴露SCS质量块以释放MEMS结构。

42. 发明申请

US20110104844A1 METHOD FOR FABRICATING MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) DEVICE 有权
标题翻译：用于制造微机电系统（MEMS）器件的方法
公开(公告)号：US20110104844A1
公开(公告)日：2011-05-05
申请号：US12111208
申请日：2008-04-29
申请人： Tsung-Min Hsieh , Chien-Hsing Lee
发明人： Tsung-Min Hsieh , Chien-Hsing Lee
IPC分类号： H01L21/02
CPC分类号： B81C1/00246 , B81B2201/0235 , B81B2207/015 , B81C2203/0714 , B81C2203/0735 , G01P15/0802 , G01P15/125
摘要： A method for fabricating MEMS device includes providing a substrate having a first side and a second side. Then, a structural dielectric layer is formed over the substrate at the first side, wherein a structural conductive layer is embedded in the structural dielectric layer. A multi-stage patterning process is performed on the substrate from the second side, wherein a plurality of regions of the substrate with different levels is formed and a portion of the structural dielectric layer is exposed. An isotropic etching process is performed from the second side of the substrate or from the both side of the substrate to etch the structural dielectric layer, wherein a remaining portion of the structural dielectric layer comprises the structural conductive layer and a dielectric portion enclosed by the structural conductive layer.
摘要翻译：一种用于制造MEMS器件的方法包括提供具有第一侧和第二侧的衬底。然后，在第一侧的基板上形成结构介电层，其中结构导电层嵌入结构介电层中。从第二侧在基板上进行多级图案化处理，其中形成具有不同层次的基板的多个区域，并且结构介电层的一部分被暴露。从衬底的第二侧或从衬底的两侧进行各向同性蚀刻工艺，以蚀刻结构电介质层，其中结构介电层的剩余部分包括结构导电层和由结构介电层包围的电介质部分导电层。

43. 发明申请

US20100330722A1 CMOS MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译： CMOS微电子机电系统（MEMS）器件及其制造方法
公开(公告)号：US20100330722A1
公开(公告)日：2010-12-30
申请号：US12490318
申请日：2009-06-24
申请人： Tsung-Min Hsieh , Chien-Hsing Lee
发明人： Tsung-Min Hsieh , Chien-Hsing Lee
IPC分类号： H01L21/30
CPC分类号： B81C1/00246 , B81B2201/0235 , B81C2203/0714 , G01L9/0042 , G01P15/0802 , G01P15/125 , G01P2015/0828
摘要： A method for fabricating the MEMS device includes providing a substrate. Then, a structural dielectric layer is formed over the substrate at a first side, wherein a diaphragm is embedded in the structural dielectric layer. The substrate is patterned from a second side to form a cavity in corresponding to the diaphragm and a plurality of venting holes in the substrate. An isotropic etching process is performed from the first side and the second side of the substrate via vent holes to remove a dielectric portion of the structural dielectric layer for exposing a central portion of the diaphragm while an end portion is held by a residue portion of the structural dielectric layer.
摘要翻译：一种用于制造MEMS器件的方法包括提供衬底。然后，在第一面上在基板上形成结构介电层，其中隔膜嵌入在结构介电层中。衬底从第二侧构图，以形成对应于隔膜的空腔和衬底中的多个排气孔。从衬底的第一侧和第二侧经由通气孔进行各向同性蚀刻处理，以去除结构介质层的电介质部分，用于暴露隔膜的中心部分，同时端部被残留部分保持结构介电层。

44. 发明授权

US07200038B2 Nonvolatile memory structure 有权
标题翻译：非易失性存储器结构
公开(公告)号：US07200038B2
公开(公告)日：2007-04-03
申请号：US11162731
申请日：2005-09-21
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3468
摘要： The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.
摘要翻译：本发明涉及非易失性存储器件的布局。存储单元具有栅电极，第一掺杂电极和第二掺杂电极。第一掺杂电极耦合到位线。栅电极耦合到一个分离的字线。共享耦合电容器结构耦合在来自第二掺杂电极的相邻位线的所有存储单元之间。电容器结构具有至少两个浮栅MOS电容器。每个浮栅MOS电容器具有浮置晶体管，其具有浮置栅极，第一S / D区域和第二S / D区域; 以及耦合到浮动栅极的MOS电容器。第一S / D区域耦合到相应一个晶体管存储单元的第二掺杂电极，并且第二S / D区域与浮置栅晶体管的相邻一个共享。

45. 发明申请

US20060067124A1 NONVOLATILE MEMORY STRUCTURE 有权
公开(公告)号：US20060067124A1
公开(公告)日：2006-03-30
申请号：US11162730
申请日：2005-09-21
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C16/04
CPC分类号： G11C16/3468
摘要： The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.

46. 发明授权

US06987298B2 Circuit layout and structure for a non-volatile memory 有权
标题翻译：非易失性存储器的电路布局和结构
公开(公告)号：US06987298B2
公开(公告)日：2006-01-17
申请号：US10823488
申请日：2004-04-12
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： H01L29/792
CPC分类号： G11C16/0491 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/42328 , H01L29/42344 , H01L29/7887 , H01L29/7923
摘要： A structure of non-volatile memory contains a substrate. A plurality of bit lines are formed in the substrate along a first direction, wherein each of the bit lines also serve as a source/drain (S/D) region. A first dielectric layer is disposed over the substrate. A plurality of selection gate (SG) lines are formed over the first dielectric layer between the bit lines. A plurality of charge-storage structure layer are formed over the substrate between the bit lines and the SG lines. A second dielectric layer is formed over the SG lines and a third dielectric layer is formed over the bit lines. A plurality of word lines are formed over the substrate along a second direction, which is crossing the first direction for the bit lines. Wherein, when a selected one of the SG lines is applied a voltage, another S/D region is created in the substrate under the selected one of the SG lines.
摘要翻译：非易失性存储器的结构包含衬底。沿着第一方向在衬底中形成多个位线，其中每个位线还用作源极/漏极（S / D）区域。第一电介质层设置在衬底上。在位线之间的第一电介质层上形成多个选择栅（SG）线。在位线和SG线之间的衬底上形成多个电荷存储结构层。在SG线上形成第二电介质层，并且在位线之上形成第三介电层。沿着与位线的第一方向交叉的第二方向在基板上形成多个字线。其中，当所选择的一条SG线施加电压时，在所选择的一条SG线之下的衬底中产生另一S / D区。

47. 发明申请

US20050265077A1 Circuit layout and structure for a non-volatile memory 审中-公开
标题翻译：非易失性存储器的电路布局和结构
公开(公告)号：US20050265077A1
公开(公告)日：2005-12-01
申请号：US11196037
申请日：2005-08-02
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C11/34 , G11C16/04 , H01L21/8246 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0491 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/42328 , H01L29/42344 , H01L29/7887 , H01L29/7923
摘要： A structure of non-volatile memory contains a substrate. A plurality of bit lines are formed in the substrate along a first direction, wherein each of the bit lines also serve as a source/drain (S/D) region. A first dielectric layer is disposed over the substrate. A plurality of selection gate (SG) lines are formed over the first dielectric layer between the bit lines. A plurality of charge-storage structure layer are formed over the substrate between the bit lines and the SG lines. A second dielectric layer is formed over the SG lines and a third dielectric layer is formed over the bit lines. A plurality of word lines are formed over the substrate along a second direction, which is crossing the first direction for the bit lines. Wherein, when a selected one of the SG lines is applied a voltage, another S/D region is created in the substrate under the selected one of the SG lines.
摘要翻译：非易失性存储器的结构包含衬底。沿着第一方向在衬底中形成多个位线，其中每个位线还用作源极/漏极（S / D）区域。第一电介质层设置在衬底上。在位线之间的第一电介质层上形成多个选择栅（SG）线。在位线和SG线之间的衬底上形成多个电荷存储结构层。在SG线上形成第二电介质层，并且在位线之上形成第三介电层。沿着与位线的第一方向交叉的第二方向在基板上形成多个字线。其中，当所选择的一条SG线施加电压时，在所选择的一条SG线之下的衬底中产生另一S / D区。

48. 发明申请

US20050237777A1 Nonvolatile memory device and method for fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20050237777A1
公开(公告)日：2005-10-27
申请号：US10987045
申请日：2004-11-12
申请人： Tsung-Min Hsieh , Jhyy-Cheng Liou , Chien-Hsing Lee , Chin-Hsi Lin
发明人： Tsung-Min Hsieh , Jhyy-Cheng Liou , Chien-Hsing Lee , Chin-Hsi Lin
IPC分类号： G11C16/04 , H01L21/8246 , H01L27/115
CPC分类号： G11C16/0491 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A structure of non-volatile memory has a plurality of buried bit lines in a substrate, extending along a first direction. Selection gate structure lines are located between the buried bit lines. A plurality of stack dielectric films on the both sides of the selection gate structure lines serving as a charge storage region, does not extend to the bit lines and a dielectric layer contacting a surface of substrate adjacent to stacked dielectric films. Word lines are over the substrate, wherein stacked dielectric films and a dielectric layer are interposed between WL and substrate on the region excluding the selection gate structure line, extending along a second direction different from the first direction. Since the charge storage layer does not completely cover between the selection gate structure lines and the bit lines, an additional control gate is formed.
摘要翻译：非易失性存储器的结构在衬底中具有沿着第一方向延伸的多个掩埋位线。选择栅极结构线位于掩埋位线之间。在用作电荷存储区域的选择栅极结构线的两侧上的多个堆叠电介质膜不延伸到位线，并且电介质层与基板的与堆叠的电介质膜相邻的表面接触。字线在衬底上方，其中堆叠的电介质膜和电介质层插入在除了选择栅极结构线之外的区域之间的WL和衬底之间，沿着不同于第一方向的第二方向延伸。由于电荷存储层不完全覆盖在选择栅极结构线和位线之间，所以形成附加的控制栅极。

49. 发明申请

US20050146932A1 [NONVOLATILE MEMORY STRUCTURE] 有权
标题翻译： [非易失性存储器结构]
公开(公告)号：US20050146932A1
公开(公告)日：2005-07-07
申请号：US10707665
申请日：2003-12-31
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C16/04 , G11C16/34
CPC分类号： G11C16/3468
摘要： The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.
摘要翻译：本发明涉及非易失性存储器件的布局。存储单元具有栅电极，第一掺杂电极和第二掺杂电极。第一掺杂电极耦合到位线。栅电极耦合到一个分离的字线。共享耦合电容器结构耦合在来自第二掺杂电极的相邻位线的所有存储单元之间。电容器结构具有至少两个浮栅MOS电容器。每个浮栅MOS电容器具有浮置晶体管，其具有浮置栅极，第一S / D区域和第二S / D区域; 以及耦合到浮动栅极的MOS电容器。第一S / D区域耦合到相应一个晶体管存储单元的第二掺杂电极，并且第二S / D区域与浮置栅晶体管的相邻一个共享。

50. 发明授权

US08987842B2 Microelectromechanical system (MEMS) device and fabrication method thereof 有权
标题翻译：微机电系统（MEMS）器件及其制造方法
公开(公告)号：US08987842B2
公开(公告)日：2015-03-24
申请号：US13615645
申请日：2012-09-14
申请人： Tsung-Min Hsieh , Chien-Hsing Lee , Jhyy-Cheng Liou
发明人： Tsung-Min Hsieh , Chien-Hsing Lee , Jhyy-Cheng Liou
IPC分类号： H01L29/84 , B81B3/00 , B81B7/00 , B81C1/00
CPC分类号： B81C1/00158 , B81B3/00 , B81B3/0013 , B81B7/00 , B81B2201/0257 , B81C1/00 , B81C1/00952 , H04R19/005 , H04R2201/003
摘要： A MEMS device includes a silicon substrate and a structural dielectric layer. The silicon substrate has a cavity. The structural dielectric layer is disposed on the silicon substrate. The structural dielectric layer has a space above the cavity of the silicon substrate and holds a plurality of structure elements within the space, including: a conductive backplate, over the silicon substrate, having a plurality of venting holes and a plurality of protrusion structures on top of the conductive backplate; and a diaphragm, located above the conductive backplate by a distance, wherein a chamber is formed between the diaphragm and the conductive backplate, and is connected to the cavity of the silicon substrate through the venting holes. A first side of the diaphragm is exposed by the chamber and faces to the protrusion structures of the conductive backplate and a second side of the diaphragm is exposed to an environment space.
摘要翻译： MEMS器件包括硅衬底和结构介电层。硅衬底具有空腔。结构介电层设置在硅衬底上。所述结构介电层在所述硅衬底的空腔上方具有空间，并且在所述空间内保持多个结构元件，所述结构元件包括：在所述硅衬底上的导电背板，具有多个通气孔和顶部的多个突出结构的导电背板; 以及隔膜，位于导电背板上方一段距离处，其中在隔膜和导电背板之间形成腔室，并且通过排气孔与硅衬底的空腔连接。隔膜的第一侧由腔室暴露，并面向导电背板的突出结构，并且隔膜的第二侧暴露于环境空间。

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