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41. 发明授权

US08605086B2 Hybrid multisample/supersample antialiasing 有权
标题翻译：混合多采样/超采样抗锯齿
公开(公告)号：US08605086B2
公开(公告)日：2013-12-10
申请号：US12167997
申请日：2008-07-03
申请人： Cass W. Everitt , Steven E. Molnar
发明人： Cass W. Everitt , Steven E. Molnar
IPC分类号： G06T15/50
CPC分类号： G06T11/40
摘要： A system and method for dynamically adjusting the pixel sampling rate during primitive shading can improve image quality or increase shading performance. Hybrid antialiasing is performed by selecting a number of shaded samples per pixel fragment. A combination of supersample and multisample antialiasing is used where a cluster of sub-pixel samples (multisamples) is processed for each pass through a fragment shader pipeline. The number of shader passes and multisamples in each cluster can be determined dynamically for each primitive based on rendering state.
摘要翻译：在原始着色中动态调整像素采样率的系统和方法可以提高图像质量或增加遮蔽性能。通过选择每个像素片段的阴影样本数来执行混合抗混叠。使用超采样和多采样抗锯齿的组合，其中对于通过片段着色器管线的每次通过处理子像素采样（多采样）的簇。可以基于呈现状态为每个基元动态地确定每个集群中的着色器遍数和多个样本的数量。

42. 发明申请

US20130300754A1 CULL STREAMS FOR FINE-GRAINED RENDERING PREDICATION 审中-公开
标题翻译：细粒度渲染预测的总体流程
公开(公告)号：US20130300754A1
公开(公告)日：2013-11-14
申请号：US13471383
申请日：2012-05-14
申请人： Cass W. EVERITT , Franck R. DIARD
发明人： Cass W. EVERITT , Franck R. DIARD
IPC分类号： G06T1/20
CPC分类号： G06T15/005
摘要： One embodiment of the present invention sets forth a technique to perform fine-grained rendering predication using an IGPU. A graphics driver divides a 3D object into batches of triangles. The IGPU processes each batch of triangles through a modified rendering pipeline to determine if the batch is culled. The IGPU writes bits into a bitstream corresponding to the visibility of the batches. Advantageously, this approach to rendering predication provides fine-grained culling without adding unnecessary overhead, thereby optimizing both hardware resources and performance.
摘要翻译：本发明的一个实施例提出了使用IGPU执行细粒度渲染预测的技术。图形驱动程序将3D对象分成三个三角形。 IGPU通过修改的渲染管线处理每批三角形，以确定批次是否被剔除。 IGPU将比特写入与批次的可见性相对应的比特流中。有利地，这种渲染预测的方法提供了细粒度的淘汰，而不会增加不必要的开销，从而优化硬件资源和性能。

43. 发明授权

US08319783B1 Index-based zero-bandwidth clears 有权
标题翻译：基于索引的零带宽清除
公开(公告)号：US08319783B1
公开(公告)日：2012-11-27
申请号：US12340493
申请日：2008-12-19
申请人： David Kirk McAllister , Steven E. Molnar , Peter B. Holmqvist , Jerome F. Duluk, Jr. , Cass W. Everitt , Emmett M. Kilgariff , Patrick R. Brown , Christian Johannes Amsinck
发明人： David Kirk McAllister , Steven E. Molnar , Peter B. Holmqvist , Jerome F. Duluk, Jr. , Cass W. Everitt , Emmett M. Kilgariff , Patrick R. Brown , Christian Johannes Amsinck
IPC分类号： G06T1/60 , G09G5/39 , G09G5/36 , G09G5/37
CPC分类号： G09G5/363 , G09G5/393 , G09G2360/121 , G09G2360/122
摘要： A system and method for performing zero-bandwidth-clears reduces external memory accesses by a graphics processor when performing clears and subsequent read operations. A set of clear values is stored in the graphics processor. Each portion of a color or z buffer may be configured using a zero-bandwidth-clear command to reference a clear value without writing the external memory. The clear value is provided to a requestor without accessing the external memory when a read access is performed.
摘要翻译：执行零带宽清除的系统和方法在执行清除和后续读取操作时减少图形处理器的外部存储器访问。一组清晰的值存储在图形处理器中。可以使用零带宽清除命令来配置颜色或z缓冲器的每个部分，以引用清除值而不写入外部存储器。当执行读取访问时，清除值被提供给请求者而不访问外部存储器。

44. 发明授权

US08264491B1 System, method, and computer program product for controlling a shader to gather statistics 有权
标题翻译：用于控制着色器收集统计信息的系统，方法和计算机程序产品
公开(公告)号：US08264491B1
公开(公告)日：2012-09-11
申请号：US11733066
申请日：2007-04-09
申请人： Cass W. Everitt
发明人： Cass W. Everitt
IPC分类号： G06T1/00
CPC分类号： G06T15/005
摘要： A system, method, and computer program product are provided for controlling a shader to gather statistics. In use, instructions are received utilizing a programmable interface. A shader is then controlled to gather statistics based on the instructions. Such statistics are further output to memory utilizing the shader.
摘要翻译：提供了一种系统，方法和计算机程序产品，用于控制着色器收集统计信息。在使用中，使用可编程接口接收指令。然后控制着色器以根据说明收集统计信息。使用着色器将这种统计信息进一步输出到存储器。

45. 发明申请

US20120147027A1 METHOD AND SYSTEM FOR IMPROVING DATA COHERENCY IN A PARALLEL RENDERING SYSTEM 有权
标题翻译：用于提高并行渲染系统中的数据相关性的方法和系统
公开(公告)号：US20120147027A1
公开(公告)日：2012-06-14
申请号：US13399458
申请日：2012-02-17
申请人： Steven E. MOLNAR , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. MOLNAR , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

46. 发明授权

US08094158B1 Using programmable constant buffers for multi-threaded processing 有权
标题翻译：使用可编程常量缓冲区进行多线程处理
公开(公告)号：US08094158B1
公开(公告)日：2012-01-10
申请号：US11344306
申请日：2006-01-31
申请人： Roger L. Allen , Cass W. Everitt , Henry P. Moreton , Thomas H. Kong
发明人： Roger L. Allen , Cass W. Everitt , Henry P. Moreton , Thomas H. Kong
IPC分类号： G06F13/00
CPC分类号： G06F9/3832 , G06F9/3851 , G06F12/0292 , G06T1/20
摘要： Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.
摘要翻译：在多线程处理器中使用多个版本的可编程常数的系统和方法允许在使用常数的程序完成执行之前更改可编程常数。可以提高处理性能，因为对可编程常数使用不同值的程序可以同时执行。可编程常数存储在常量缓冲区中，常数缓冲表的条目被绑定到常量缓冲区。当可编程常数被更改时，它被复制到页面池中的条目，并且页面池的地址转换被更新为对应于可编程常数的旧版本（复制）。一个优点是常量缓冲存储最新版本的可编程常数。

47. 发明授权

US08085272B1 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08085272B1
公开(公告)日：2011-12-27
申请号：US11556657
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种方法，其包括以下步骤：接收公共输入流，跟踪与公共输入流相关联的周期性事件，从公共输入流生成多个片段流，插入标记基于所述多个片段流中的第一片段流中的所述周期性事件的发生，并且利用所述标记来影响所述第一片段流的处理，使得多个光栅操作（ROP）请求流保持基本相同的一致性公共输入流。每个片段流被独立地处理并对应于其中一个ROP请求流。

48. 发明授权

US07999820B1 Methods and systems for reusing memory addresses in a graphics system 有权
标题翻译：在图形系统中重复使用存储器地址的方法和系统
公开(公告)号：US07999820B1
公开(公告)日：2011-08-16
申请号：US11953812
申请日：2007-12-10
申请人： Adam Clark Weitkemper , Steven E. Molnar , Mark J. French , Cass W. Everitt
发明人： Adam Clark Weitkemper , Steven E. Molnar , Mark J. French , Cass W. Everitt
IPC分类号： G06F12/02 , G06F12/10 , G06F12/06
CPC分类号： G06F12/0223 , G06F12/10 , G09G5/39 , G09G2360/122
摘要： Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint on a display screen to a group of contiguous physical memory locations in a memory system, determining an anchor physical memory address from a first transaction associated with the footprint, wherein the anchor physical memory address corresponds to an anchor in the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits (LSBs) associated with the second transaction, and combining the anchor physical memory address with the set of LSBs associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.
摘要翻译：公开了用于重新使用图形系统中的存储器地址的方法和系统，从而可以减少地址转换硬件的实例。本发明的一个实施例提出了一种方法，其包括将显示屏幕上的占位面积映射到存储器系统中的一组连续物理存储器位置，从与所述覆盖区相关联的第一事务确定锚物理存储器地址，其中，锚物理存储器地址对应于连续物理存储器位置组中的锚点，确定也与占用空间相关联的第二事务，确定与第二事务相关联的一组最低有效位（LSB），以及组合锚物理存储器地址与与第二事务相关联的一组LSB产生用于第二事务的第二物理存储器地址，从而避免第二次完全地址转换。

49. 发明授权

US07886116B1 Bandwidth compression for shader engine store operations 有权
标题翻译：着色引擎存储操作的带宽压缩
公开(公告)号：US07886116B1
公开(公告)日：2011-02-08
申请号：US11830778
申请日：2007-07-30
申请人： Cass W. Everitt
发明人： Cass W. Everitt
IPC分类号： G06F12/00 , G06F17/00 , G06K9/36
CPC分类号： G06F9/30043 , G06F2212/401
摘要： Embodiments of the present invention set forth systems and methods for compressing thread group data written to frame buffer memory to increase overall memory performance. A compression/decompression engine within the frame buffer memory interface includes logic configured to identify situations where the threads of a thread group are writing similar scalar values to memory. Upon recognizing such a situation, the engine is configured to compress the scalar data into a form that allows all of the scalar data to be written to or read from the frame buffer memory in fewer clock cycles than would be required to transmit the data in uncompressed form to or from memory. Consequently, the disclosed systems and methods are able to effectively increase memory performance when executing thread group STORE and LOAD operations.
摘要翻译：本发明的实施例提出了将写入帧缓冲存储器的线程组数据压缩以增加总体存储器性能的系统和方法。帧缓冲存储器接口内的压缩/解压缩引擎包括被配置为识别线程组的线程将相似标量值写入存储器的情况的逻辑。在识别到这种情况之后，引擎被配置为将标量数据压缩成允许所有标量数据以比未压缩的数据传输所需的更少的时钟周期写入或从帧缓冲存储器读取的形式形式到或来自记忆。因此，所公开的系统和方法能够在执行线程组存储和加载操作时有效地增加存储器性能。

50. 发明授权

US07868891B2 Load balancing 有权
标题翻译：负载均衡
公开(公告)号：US07868891B2
公开(公告)日：2011-01-11
申请号：US11229458
申请日：2005-09-16
申请人： Daniel Elliot Wexler , Larry I. Gritz , Eric B. Enderton , Cass W. Everitt
发明人： Daniel Elliot Wexler , Larry I. Gritz , Eric B. Enderton , Cass W. Everitt
IPC分类号： G06F15/16 , G06T15/00
CPC分类号： G06T15/005 , G06F9/505 , G06F9/5066 , G06F2209/509 , G06T1/20
摘要： Embodiments of methods, apparatuses, devices, and/or systems for load balancing two processors, such as for graphics and/or video processing, for example, are described.
摘要翻译：对例如用于图形和/或视频处理的两个处理器的负载平衡的方法，装置，设备和/或系统的实施例进行了描述。

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