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41. 发明授权

US09269042B2 Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices 有权
标题翻译：使用相变突触装置在神经元网络中产生尖峰时间依赖性可塑性
公开(公告)号：US09269042B2
公开(公告)日：2016-02-23
申请号：US12895791
申请日：2010-09-30
申请人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04 , G11C11/54 , G11C13/00
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
摘要翻译：本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

42. 发明授权

US08832011B2 Electronic synapses from stochastic binary memory devices 有权
公开(公告)号：US08832011B2
公开(公告)日：2014-09-09
申请号：US13611722
申请日：2012-09-12
申请人： Bipin Rajendran , Mark B. Ritter
发明人： Bipin Rajendran , Mark B. Ritter
IPC分类号： G06N3/04 , G06N3/00 , G06N3/063
CPC分类号： G06N3/0635 , G06N3/04 , G06N3/049
摘要： According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.

43. 发明申请

US20140078837A1 COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT 有权
标题翻译：紧凑型低功耗异步电动势记忆读取操作和电路
公开(公告)号：US20140078837A1
公开(公告)日：2014-03-20
申请号：US13552932
申请日：2012-07-19
申请人： SEONGWON KIM , Yong Liu , Bipin Rajendran
发明人： SEONGWON KIM , Yong Liu , Bipin Rajendran
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/067 , G11C11/5678 , G11C13/0004
摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.
摘要翻译：紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。读出放大器读取存储单元的状态。感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器状态。

44. 发明授权

US08466006B2 Thermally insulated phase material cells 有权
标题翻译：绝热相材料电池
公开(公告)号：US08466006B2
公开(公告)日：2013-06-18
申请号：US13363549
申请日：2012-02-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L21/16 , H01L21/44
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译：一种存储单元结构及其形成方法。该方法包括在电介质层内形成孔。孔形成在导电底部电极的中心上方。该方法包括沿孔的至少一个侧壁沉积绝热层。绝热层将热量从相变电流隔离成孔的体积。在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。该方法还包括在相变材料上形成导电顶电极。

45. 发明申请

US20120126194A1 THERMALLY INSULATED PHASE CHANGE MATERIAL MEMORY CELLS 有权
标题翻译：热绝缘相变材料记忆细胞
公开(公告)号：US20120126194A1
公开(公告)日：2012-05-24
申请号：US13364153
申请日：2012-02-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译：一种存储单元结构及其形成方法。该方法包括在电介质层内形成孔。孔形成在导电底部电极的中心上方。该方法包括沿孔的至少一个侧壁沉积绝热层。绝热层将热量从相变电流隔离成孔的体积。在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。该方法还包括在相变材料上形成导电顶电极。

46. 发明申请

US20120084240A1 PHASE CHANGE MEMORY SYNAPTRONIC CIRCUIT FOR SPIKING COMPUTATION, ASSOCIATION AND RECALL 审中-公开
标题翻译：相位改变记忆同步电路，用于SPIKING计算，协调和调用
公开(公告)号：US20120084240A1
公开(公告)日：2012-04-05
申请号：US12895710
申请日：2010-09-30
申请人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango , Bipin Rajendran
发明人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango , Bipin Rajendran
IPC分类号： G06N3/04
CPC分类号： G06N3/063
摘要： Embodiments of the invention are directed to producing spike-timing dependent plasticity using electronic neurons for computation, and pattern matching tasks such as association and recall. In response to an electronic neuron spiking, a spiking signal is sent from the electronic neuron to each axon driver and each dendrite driver connected to the spiking electronic neuron. Each axon driver receiving the spiking signal sends an axonal signal from the axon driver to a variable state resistor. Each dendrite driver receiving the spiking signal sends a dendritic signal from the dendrite driver to the variable state resistor, wherein the variable state resistor couples the axon driver and the dendrite driver. The combination of the axonal and dendritic signals is capable of increasing or decreasing conductance of the variable state resistor.
摘要翻译：本发明的实施例涉及使用用于计算的电子神经元和诸如关联和召回的模式匹配任务来产生尖峰时序相关的可塑性。响应于电子神经元峰值，从电子神经元发送尖峰信号到每个轴突驱动器，并且每个枝晶驱动器连接到尖峰电子神经元。接收尖峰信号的每个轴突驱动器将轴突信号从轴突驱动器发送到可变状态电阻器。接收尖峰信号的每个枝晶驱动器将枝晶信号从枝晶驱动器发送到可变状态电阻器，其中可变状态电阻器耦合轴突驱动器和枝晶驱动器。轴突和树突状信号的组合能够增加或降低可变状态电阻的电导。

47. 发明授权

US08120937B2 Ternary content addressable memory using phase change devices 有权
标题翻译：使用相变装置的三元内容可寻址存储器
公开(公告)号：US08120937B2
公开(公告)日：2012-02-21
申请号：US12399346
申请日：2009-03-06
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C10/00 , G11C11/00 , G11C11/56
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译：一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。第一和第二存储器元件以并联电路电耦合到匹配线。第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。

48. 发明授权

US08116126B2 Measurement method for reading multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition 失效
标题翻译：使用测量时间延迟读取多级存储单元作为电平定义的特征参数的测量方法
公开(公告)号：US08116126B2
公开(公告)日：2012-02-14
申请号：US12542146
申请日：2009-08-17
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： A memory system includes a memory cell configured to represent at least two binary values, a bit line coupled to the memory cell, and first and second comparators coupled to the bit line that, respectively, compare a first and second reference value to a value of a parameter of the bit-line. The system also includes a first and second timers configured to measures a time for the parameter of the bit line to decay. The system also includes a logic unit coupled to the first and second timers that selects the time for the parameter of the bit line to decay from to a first value or a second value.
摘要翻译：存储器系统包括被配置为表示至少两个二进制值的存储器单元，耦合到存储单元的位线，以及耦合到位线的第一和第二比较器，其分别将第一和第二参考值与位线的参数。该系统还包括配置成测量位线参数衰减的时间的第一和第二定时器。该系统还包括耦合到第一和第二定时器的逻辑单元，其选择位线的参数从第一值或第二值衰减的时间。

49. 发明授权

US08107276B2 Resistive memory devices having a not-and (NAND) structure 有权
标题翻译：具有非 - 和（NAND）结构的电阻式存储器件
公开(公告)号：US08107276B2
公开(公告)日：2012-01-31
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

50. 发明申请

US20110153533A1 PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN AN ULTRA-DENSE SYNAPSE CROSS-BAR ARRAY 有权
标题翻译：在超声波同步串联阵列阵列中产生依赖时间的塑性
公开(公告)号：US20110153533A1
公开(公告)日：2011-06-23
申请号：US12645479
申请日：2009-12-22
申请人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
发明人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
IPC分类号： G06N3/02
CPC分类号： G06N3/049 , G06N3/0635
摘要： Embodiments of the invention relate to producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array for neuromorphic systems. An aspect of the invention includes when an electronic neuron spikes, an alert pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When the spiking electronic neuron sends the alert pulse, a gate pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When each electronic neuron receives the alert pulse, a response pulse is sent from each electronic neuron receiving the alert pulse to the spiking electronic neuron. The response pulse is a function of time since a last spiking of the electronic neuron receiving the alert pulse. In addition, the combination of the gate pulse and response pulse is capable increasing or decreasing conductance of a variable state resistor.
摘要翻译：本发明的实施方案涉及在用于神经形态系统的超密集突触交叉阵列中产生尖峰时间依赖性可塑性。本发明的一个方面包括当电子神经元尖峰时，警报脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当尖峰电子神经元发出警报脉冲时，门脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当每个电子神经元接收到警报脉冲时，从接收警报脉冲的每个电子神经元发送响应脉冲到尖峰电子神经元。响应脉冲是从接收警报脉冲的电子神经元的最后一次尖峰起的时间的函数。此外，门脉冲和响应脉冲的组合能够增加或降低可变状态电阻器的电导。

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