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1. 发明申请

US20120084240A1 PHASE CHANGE MEMORY SYNAPTRONIC CIRCUIT FOR SPIKING COMPUTATION, ASSOCIATION AND RECALL 审中-公开
标题翻译：相位改变记忆同步电路，用于SPIKING计算，协调和调用
公开(公告)号：US20120084240A1
公开(公告)日：2012-04-05
申请号：US12895710
申请日：2010-09-30
申请人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango , Bipin Rajendran
发明人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango , Bipin Rajendran
IPC分类号： G06N3/04
CPC分类号： G06N3/063
摘要： Embodiments of the invention are directed to producing spike-timing dependent plasticity using electronic neurons for computation, and pattern matching tasks such as association and recall. In response to an electronic neuron spiking, a spiking signal is sent from the electronic neuron to each axon driver and each dendrite driver connected to the spiking electronic neuron. Each axon driver receiving the spiking signal sends an axonal signal from the axon driver to a variable state resistor. Each dendrite driver receiving the spiking signal sends a dendritic signal from the dendrite driver to the variable state resistor, wherein the variable state resistor couples the axon driver and the dendrite driver. The combination of the axonal and dendritic signals is capable of increasing or decreasing conductance of the variable state resistor.
摘要翻译：本发明的实施例涉及使用用于计算的电子神经元和诸如关联和召回的模式匹配任务来产生尖峰时序相关的可塑性。响应于电子神经元峰值，从电子神经元发送尖峰信号到每个轴突驱动器，并且每个枝晶驱动器连接到尖峰电子神经元。接收尖峰信号的每个轴突驱动器将轴突信号从轴突驱动器发送到可变状态电阻器。接收尖峰信号的每个枝晶驱动器将枝晶信号从枝晶驱动器发送到可变状态电阻器，其中可变状态电阻器耦合轴突驱动器和枝晶驱动器。轴突和树突状信号的组合能够增加或降低可变状态电阻的电导。

2. 发明申请

US20120259804A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 有权
公开(公告)号：US20120259804A1
公开(公告)日：2012-10-11
申请号：US13083414
申请日：2011-04-08
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

3. 发明申请

US20120109863A1 CANONICAL SPIKING NEURON NETWORK FOR SPATIOTEMPORAL ASSOCIATIVE MEMORY 有权
公开(公告)号：US20120109863A1
公开(公告)日：2012-05-03
申请号：US12828091
申请日：2010-06-30
申请人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango
发明人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango
IPC分类号： G06N3/063 , G06N3/08
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to canonical spiking neurons for spatiotemporal associative memory. An aspect of the invention provides a spatiotemporal associative memory including a plurality of electronic neurons having a layered neural net relationship with directional synaptic connectivity. The plurality of electronic neurons configured to detect the presence of a spatiotemporal pattern in a real-time data stream, and extract the spatiotemporal pattern. The plurality of electronic neurons are further configured to, based on learning rules, store the spatiotemporal pattern in the plurality of electronic neurons, and upon being presented with a version of the spatiotemporal pattern, retrieve the stored spatiotemporal pattern.

4. 发明授权

US08898097B2 Reconfigurable and customizable general-purpose circuits for neural networks 有权
标题翻译：可重构和可定制的神经网络通用电路
公开(公告)号：US08898097B2
公开(公告)日：2014-11-25
申请号：US13587594
申请日：2012-08-16
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

5. 发明授权

US08856055B2 Reconfigurable and customizable general-purpose circuits for neural networks 有权
公开(公告)号：US08856055B2
公开(公告)日：2014-10-07
申请号：US13083414
申请日：2011-04-08
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

6. 发明申请

US20120317062A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 有权
标题翻译：神经网络可重构和可定制的一般用途电路
公开(公告)号：US20120317062A1
公开(公告)日：2012-12-13
申请号：US13587594
申请日：2012-08-16
申请人： Bernard V. BREZZO , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. BREZZO , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/08
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

7. 发明授权

US09665822B2 Canonical spiking neuron network for spatiotemporal associative memory 有权
公开(公告)号：US09665822B2
公开(公告)日：2017-05-30
申请号：US12828091
申请日：2010-06-30
申请人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango
发明人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango
IPC分类号： G06F15/18 , G06N3/08 , G06N3/04 , G06N3/063
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to canonical spiking neurons for spatiotemporal associative memory. An aspect of the invention provides a spatiotemporal associative memory including a plurality of electronic neurons having a layered neural net relationship with directional synaptic connectivity. The plurality of electronic neurons configured to detect the presence of a spatiotemporal pattern in a real-time data stream, and extract the spatiotemporal pattern. The plurality of electronic neurons are further configured to, based on learning rules, store the spatiotemporal pattern in the plurality of electronic neurons, and upon being presented with a version of the spatiotemporal pattern, retrieve the stored spatiotemporal pattern.

8. 发明申请

US20120330872A1 CANONICAL SPIKING NEURON NETWORK FOR SPATIOTEMPORAL ASSOCIATIVE MEMORY 审中-公开
标题翻译：经典SPIKING神经网络的空间相关记忆
公开(公告)号：US20120330872A1
公开(公告)日：2012-12-27
申请号：US13598915
申请日：2012-08-30
申请人： Steven K. ESSER , Dharmendra S. Modha , Anthony Ndirango
发明人： Steven K. ESSER , Dharmendra S. Modha , Anthony Ndirango
IPC分类号： G06N3/08
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to canonical spiking neurons for spatiotemporal associative memory. An aspect of the invention provides a spatiotemporal associative memory including a plurality of electronic neurons having a layered neural net relationship with directional synaptic connectivity. The plurality of electronic neurons configured to detect the presence of a spatiotemporal pattern in a real-time data stream, and extract the spatiotemporal pattern. The plurality of electronic neurons are further configured to, based on learning rules, store the spatiotemporal pattern in the plurality of electronic neurons, and upon being presented with a version of the spatiotemporal pattern, retrieve the stored spatiotemporal pattern.
摘要翻译：本发明的实施例涉及用于时空关联记忆的规范加标神经元。本发明的一个方面提供了包括具有与定向突触连通性的分层神经网络关系的多个电子神经元的时空相关存储器。多个电子神经元被配置为检测实时数据流中的时空模式的存在，并提取时空模式。多个电子神经元还被配置为基于学习规则将时空图案存储在多个电子神经元中，并且在呈现时空图案的版本时，检索存储的时空图案。

9. 发明授权

US09524462B2 Canonical spiking neuron network for spatiotemporal associative memory 有权
标题翻译：用于时空联想记忆的典型加标神经元网络
公开(公告)号：US09524462B2
公开(公告)日：2016-12-20
申请号：US13598915
申请日：2012-08-30
申请人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango
发明人： Steven K. Esser , Dharmendra S. Modha , Anthony Ndirango
IPC分类号： G06F15/18 , G06N3/08 , G06N3/04 , G06N3/063
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to canonical spiking neurons for spatiotemporal associative memory. An aspect of the invention provides a spatiotemporal associative memory including a plurality of electronic neurons having a layered neural net relationship with directional synaptic connectivity. The plurality of electronic neurons configured to detect the presence of a spatiotemporal pattern in a real-time data stream, and extract the spatiotemporal pattern. The plurality of electronic neurons are further configured to, based on learning rules, store the spatiotemporal pattern in the plurality of electronic neurons, and upon being presented with a version of the spatiotemporal pattern, retrieve the stored spatiotemporal pattern.
摘要翻译：本发明的实施例涉及用于时空关联记忆的规范加标神经元。本发明的一个方面提供了包括具有与定向突触连通性的分层神经网络关系的多个电子神经元的时空相关存储器。多个电子神经元被配置为检测实时数据流中的时空模式的存在，并提取时空模式。多个电子神经元还被配置为基于学习规则将时空图案存储在多个电子神经元中，并且在呈现时空图案的版本时，检索存储的时空图案。

10. 发明授权

US08589320B2 Area efficient neuromorphic system that connects a FET in a diode configuration, and a variable resistance material to junctions of neuron circuit blocks 有权
标题翻译：将二极管配置中的FET和可变电阻材料连接到神经元电路块的结的区域有效的神经元系统
公开(公告)号：US08589320B2
公开(公告)日：2013-11-19
申请号：US13548532
申请日：2012-07-13
申请人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
IPC分类号： G06E1/00
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic system includes a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks. The plurality of synapse blocks includes a plurality of neuromorphic circuits. Each neuromorphic circuit includes a field effect transistor in a diode configuration electrically connected to variable resistance material, where the variable resistance material provides a programmable resistance value. Each neuromorphic circuit also includes a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks, and a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks.
摘要翻译：神经元系统包括电连接到多个神经元电路块的多个突触块。多个突触块包括多个神经形态电路。每个神经形态电路包括电连接到可变电阻材料的二极管配置中的场效应晶体管，其中可变电阻材料提供可编程电阻值。每个神经形态电路还包括电连接到可变电阻材料的第一结和一个或多个神经元电路块的输出，以及电连接到场效应晶体管的第二结和一个或多个神经元电路的输入块。

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