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1. 发明申请

US20110134676A1 RESISTIVE MEMORY DEVICES HAVING A NOT-AND (NAND) STRUCTURE 有权
标题翻译：具有非和（非）结构的电阻式存储器件
公开(公告)号：US20110134676A1
公开(公告)日：2011-06-09
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C7/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

2. 发明授权

US08107276B2 Resistive memory devices having a not-and (NAND) structure 有权
标题翻译：具有非 - 和（NAND）结构的电阻式存储器件
公开(公告)号：US08107276B2
公开(公告)日：2012-01-31
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

3. 发明授权

US08023345B2 Iteratively writing contents to memory locations using a statistical model 有权
标题翻译：使用统计模型迭代地将内容写入内存位置
公开(公告)号：US08023345B2
公开(公告)日：2011-09-20
申请号：US12391693
申请日：2009-02-24
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

4. 发明授权

US08897062B2 Memory programming for a phase change memory cell 有权
标题翻译：相变存储单元的存储器编程
公开(公告)号：US08897062B2
公开(公告)日：2014-11-25
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00 , G11C13/00 , G11C29/02
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

5. 发明申请

US20110228600A1 MEMORY PROGRAMMING 有权
标题翻译：内存编程
公开(公告)号：US20110228600A1
公开(公告)日：2011-09-22
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/21
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

6. 发明申请

US20100214829A1 MEMORY PROGRAMMING 有权
标题翻译：内存编程
公开(公告)号：US20100214829A1
公开(公告)日：2010-08-26
申请号：US12391693
申请日：2009-02-24
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

7. 发明授权

US08463985B2 Constrained coding to reduce floating gate coupling in non-volatile memories 失效
标题翻译：约束编码以减少非易失性存储器中的浮动栅极耦合
公开(公告)号：US08463985B2
公开(公告)日：2013-06-11
申请号：US12751197
申请日：2010-03-31
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/02 , H03M13/00
CPC分类号： G11C16/0483 , G06F12/0246 , G06F2212/7202 , G11C7/1006 , G11C16/10
摘要： Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
摘要翻译：约束编码以减少非易失性存储器中的浮动栅极耦合，包括用于存储数据的方法。该方法包括接收要写入闪速存储器件的写入数据，响应写入数据选择一个代码字，以及将该代码字写入闪存器件。选择码字以通过防止在码字中发生指定的符号模式来减少闪存器件中的浮动栅极耦合。

8. 发明授权

US08374040B2 Write bandwidth in a memory characterized by a variable write time 有权
标题翻译：将带宽写入以可变写入时间为特征的存储器中
公开(公告)号：US08374040B2
公开(公告)日：2013-02-12
申请号：US13034936
申请日：2011-02-25
申请人： John A. Bivens , Michele M. Franceschini , Luis A. Lastras-Montano
发明人： John A. Bivens , Michele M. Franceschini , Luis A. Lastras-Montano
IPC分类号： G11C7/00
CPC分类号： G11C7/1012 , G06F2213/0038 , G11C13/0004 , G11C13/0069 , G11C2013/008
摘要： A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.
摘要翻译：一种存储器系统，其包括具有由可变写入时间表征的存储器单元的多个存储器阵列。存储器系统还包括被配置为接收写入命令的存储器总线以及被配置为与存储器阵列进行通信的多个数据缓冲器。存储器系统还包括配置为与存储器阵列通信以存储写入地址的地址缓冲器。被配置为接收写入命令并将用写入命令接收的数据线分割成多个部件的机构也包括在存储器系统中。数据线的部分存储在不同的数据缓冲器中，并且开始将写入地址的数据线的部分写入存储器阵列。当从所有存储器阵列接收到指定写入地址的写入完成信号时，写入命令完成。

9. 发明申请

US20130013886A1 ADAPTIVE WEAR LEVELING VIA MONITORING THE PROPERTIES OF MEMORY REFERENCE STREAM 有权
标题翻译：通过监测记忆参考流的性质，自适应磨损
公开(公告)号：US20130013886A1
公开(公告)日：2013-01-10
申请号：US13619513
申请日：2012-09-14
申请人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F2212/1052 , G06F2212/7201 , G06F2212/7211
摘要： Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses.
摘要翻译：在有限寿命的存储器设备中的自适应写平均化，包括执行用于监视包括写入行地址的写入数据流的方法。检测写入数据流的属性，并响应于检测到的属性来调整写入调平过程。写入平均过程被应用于写入数据流以从写入地址生成物理地址。

10. 发明申请

US20130013860A1 MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 有权
标题翻译：用于改善记忆性能的存储单元预置
公开(公告)号：US20130013860A1
公开(公告)日：2013-01-10
申请号：US13619451
申请日：2012-09-14
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.
摘要翻译：用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值存储器单元的指定状态到存储器单元的期望状态。第二期望值比第一期望值更接近写入性能特性的期望值。区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

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