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31. 发明授权

US08350609B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08350609B2
公开(公告)日：2013-01-08
申请号：US13369063
申请日：2012-02-08
申请人： Masahiro Araki , Atsuhiko Ishibashi
发明人： Masahiro Araki , Atsuhiko Ishibashi
IPC分类号： H03K5/12
CPC分类号： G11C7/1057 , G11C13/0002
摘要： The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.
摘要翻译：本发明提供一种半导体器件，其中可变电阻电路的电阻值的可调范围大。半导体器件具有包括多组电阻元件和多组晶体管，多个复制电路和多组运算放大器的输出缓冲器，并且调节多组晶体管的漏极电流使得输出缓冲器的输出阻抗变为预定值。因此，即使在电阻元件的电阻值由于制造工艺等的波动而大幅波动的情况下，也可以将输出阻抗设定为规定值。

32. 发明授权

US08324943B1 High voltage linear amplifier driving heavy capacitive loads with reduced power dissipation 有权
标题翻译：高电压线性放大器驱动大容量负载，降低功耗
公开(公告)号：US08324943B1
公开(公告)日：2012-12-04
申请号：US12571340
申请日：2009-09-30
申请人： Anindya Bhattacharya , John Melanson
发明人： Anindya Bhattacharya , John Melanson
IPC分类号： H03K5/12 , H03K17/04 , B41J29/38
CPC分类号： B41J2/04541 , B41J2/04548 , B41J2/0455 , B41J2/04581 , H03K4/063 , H03K5/12
摘要： A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.
摘要翻译：容性负载驱动电路可以包括高电流驱动放大器，其被配置为在跨过容性负载的电压的高电流斜坡上升到截止电压时耦合到电容性负载; 低电流驱动放大器被配置为在跨过容性负载的电压的低电流斜升期间从截止电压到跨过容性负载的最大电压连接到电容性负载; 以及高电流驱动放大器，被配置为在跨过容性负载的电压的高电流斜降期间连接到电容性负载。在电容负载两端的电压稳定期间，低电流驱动放大器可以连接到电容性负载，低电平斜坡上升和高电流斜坡下降。

33. 发明授权

US08179076B2 Chip structure capable of smoothing slope of signal during conversion 有权
标题翻译：芯片结构能够在转换期间平滑信号的斜率
公开(公告)号：US08179076B2
公开(公告)日：2012-05-15
申请号：US12149698
申请日：2008-05-07
申请人： Lu-Yueh Hsu
发明人： Lu-Yueh Hsu
IPC分类号： H03K5/12 , G03B13/00 , H01L27/00
CPC分类号： H03K19/00361 , H02P25/034
摘要： The present invention discloses a chip structure capable of smoothing slope of signal during conversion. And the chip structure is suitable for a DC motor which is embedded in a portable electronic device. The DC motor is for adjusting the focal distance of a digital camera which is installed within the portable electronic device. The chip structure comprises an input terminal, a first converter, a control unit, a second converter, an amplifier circuit and an output terminal. The input terminal is for receiving a first digital signal. The first converter is for converting the first digital signal into an analog signal. The control unit is for elongating the transform time of the analog signal. The amplifier circuit is for amplifying the elongated analog signal. The second converter is for converting the elongated analog signal into a second digital signal. And the output terminal outputs the second digital signal.
摘要翻译：本发明公开了一种能够在转换期间平滑信号斜率的芯片结构。并且芯片结构适用于嵌入在便携式电子设备中的直流电动机。直流电机用于调节安装在便携式电子设备内的数码相机的焦距。芯片结构包括输入端子，第一转换器，控制单元，第二转换器，放大器电路和输出端子。输入端用于接收第一数字信号。第一转换器用于将第一数字信号转换为模拟信号。控制单元用于延长模拟信号的变换时间。放大器电路用于放大细长的模拟信号。第二转换器用于将细长模拟信号转换成第二数字信号。输出端输出第二个数字信号。

34. 发明申请

US20120056655A1 Method and system for controlling HS-NMOS power switches with slew-rate limitation 有权
标题翻译：用于控制具有压摆率限制的HS-NMOS功率开关的方法和系统
公开(公告)号：US20120056655A1
公开(公告)日：2012-03-08
申请号：US12807769
申请日：2010-09-14
申请人： Michael Brauer , Stephan Drebinger
发明人： Michael Brauer , Stephan Drebinger
IPC分类号： H03K5/12
CPC分类号： H03K5/01 , H03K17/166 , H03K2017/6875 , H03K2217/0054
摘要： A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.
摘要翻译：公开了一种用于限制一个或多个高侧（HS）NMOS功率开关的输出电压的转换速率的方法和系统。描述配置成控制第一NMOS开关的电路装置。该装置包括电压供应装置，被配置为向第一NMOS开关的栅极端提供栅极电压; 配置为提供电流的电流供应装置; 第一控制级，被配置为提供和/或去除第一NMOS开关的栅极端子和电压供应装置之间的连接，从而分别将第一NMOS开关切换到导通状态和/或截止状态; 以及第一NMOS开关的输出端子和被配置为控制第一输出端子处的电压的转换速率的电流供应装置之间的第一反馈控制链路。

35. 发明授权

US08067969B2 Integrated circuit 失效
标题翻译：集成电路
公开(公告)号：US08067969B2
公开(公告)日：2011-11-29
申请号：US12493774
申请日：2009-06-29
申请人： Woo-Hyun Seo
发明人： Woo-Hyun Seo
IPC分类号： H03K5/12
CPC分类号： H03K19/00384
摘要： An integrated circuit includes a pull-up compensation path unit configured to adjust a pull-up driving power of an input signal; a pull-down compensation path unit configured to adjust a pull-down driving power of the input signal; and a path control unit configured to route the input signal to one of the pull-up compensation unit and the pull-down compensation unit in response to a conditional signal.
摘要翻译：集成电路包括被配置为调整输入信号的上拉驱动功率的上拉补偿路径单元; 配置为调整所述输入信号的下拉驱动功率的下拉补偿路径单元; 以及路径控制单元，被配置为响应于条件信号将输入信号路由到上拉补偿单元和下拉补偿单元中的一个。

36. 发明授权

US08040171B2 Accelerator output stage that adjusts drive duration to loading 有权
标题翻译：加速器输出级，可调整驱动持续时间加载
公开(公告)号：US08040171B2
公开(公告)日：2011-10-18
申请号：US11382995
申请日：2006-05-12
申请人： Mark B. Welty
发明人： Mark B. Welty
IPC分类号： H03K5/12
CPC分类号： H03K5/12 , H03K17/04206 , H03K17/6872 , H03K19/0016 , H03K19/00361
摘要： The accelerator output stage circuit includes: a high side output device coupled to an output node; a low side output device coupled to the output node; a first logic gate coupled to a control node of the first high side output device; a second logic gate coupled to a control node of the second high side output device; a high side one-shot device having an output coupled to a first input of the first logic gate; a low side one-shot device having an output coupled to a first input of the second logic gate; and a feedback device coupled between the output node and a second input of the first logic gate, and between the output node and a second input of the second logic gate, and between the output node and the input to the high side resistor bypass device, and between the output node and the input to the low side one-shot resistor bypass device.
摘要翻译：加速器输出级电路包括：耦合到输出节点的高侧输出装置; 耦合到所述输出节点的低侧输出装置; 耦合到所述第一高侧输出装置的控制节点的第一逻辑门; 耦合到所述第二高侧输出装置的控制节点的第二逻辑门; 具有耦合到第一逻辑门的第一输入的输出的高边单触发器件; 具有耦合到第二逻辑门的第一输入的输出的低侧单触发器件; 以及耦合在所述输出节点和所述第一逻辑门的第二输入之间以及所述输出节点和所述第二逻辑门的第二输入之间以及所述输出节点与所述高侧电阻器旁路装置的输入之间的反馈装置，并在输出节点和低端单稳态电阻旁路装置的输入之间。

37. 发明授权

US08013648B1 Output slew-rate controlled interface and method for controlling the output slew-rate of an interface 有权
标题翻译：输出转换速率控制接口和控制接口输出转换速率的方法
公开(公告)号：US08013648B1
公开(公告)日：2011-09-06
申请号：US12835166
申请日：2010-07-13
申请人： Lieh-Chiu Lin , Chun-Yu Chiu
发明人： Lieh-Chiu Lin , Chun-Yu Chiu
IPC分类号： H03K5/12
CPC分类号： H03K5/04 , H03K19/00361 , H04L25/026
摘要： An output slew-rate controlled interface is provided. The output slew-rate controlled interface includes: a standard slew-rate range generating circuit, for generating at least one standard signal defining a standard slew-rate range; a slew-rate comparing circuit, coupled to the standard slew-rate range generating circuit and a load circuit coupled to the interface, for comparing a response slew-rate of a response signal from the load circuit with the standard slew-rate range and producing a comparison result; and an outputting circuit, coupled to the slew-rate comparing circuit, for adjusting an output slew-rate of an output signal according to the comparison result and outputting the output signal to the load circuit.
摘要翻译：提供输出转换速率控制接口。输出转换速率控制接口包括：标准转换速率范围发生电路，用于产生定义标准转换速率范围的至少一个标准信号; 耦合到标准压摆率范围产生电路的转换速率比较电路和耦合到该接口的负载电路，用于将来自负载电路的响应信号的响应转换速率与标准转换速率范围进行比较，并产生比较结果; 以及输出电路，其耦合到所述转换速率比较电路，用于根据所述比较结果调整输出信号的输出转换速率，并将所述输出信号输出到所述负载电路。

38. 发明授权

US07977989B2 Method and apparatus for detecting and adjusting characteristics of a signal 失效
标题翻译：用于检测和调整信号特性的方法和装置
公开(公告)号：US07977989B2
公开(公告)日：2011-07-12
申请号：US12730671
申请日：2010-03-24
申请人： Kouros Azimi , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith
发明人： Kouros Azimi , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith
IPC分类号： H03K5/12
CPC分类号： H03K5/02 , H03K5/06 , H03K19/017581 , H04L25/0288
摘要： Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.
摘要翻译：公开了一种通过通信信道（例如，线，背板等）调整从发射机发射到接收机的信号的特性的电路。该电路包括一个锁存器，该锁存器在阈值电压施加到锁存器之后多次接收电路中预定点处的信号并对信号的电压进行多次采样。该电路还包括一个处理器，当采样电压指示转换点时，确定信号的特性，并且当采样电压不指示转换点时调整阈值电压。当信号的特性在预定范围之外时，处理器通过调节发射机的电流和电压中的至少一个来调整信号的特性。

39. 发明授权

US07956646B2 Buffer circuit and control method thereof 有权
标题翻译：缓冲电路及其控制方法
公开(公告)号：US07956646B2
公开(公告)日：2011-06-07
申请号：US12029778
申请日：2008-02-12
申请人： Hiromitsu Osawa
发明人： Hiromitsu Osawa
IPC分类号： H03K19/094 , H03K19/20 , H03K5/12
CPC分类号： H03K19/01714
摘要： The present disclosure has been worked out to provide a buffer circuit and a control method thereof capable of controlling the timing at which the output switching element is changed from an OFF state to an ON state, and preventing the output characteristic from becoming unstable. The buffer circuit includes: a driving portion 20 driving output switching elements M1 and M2; a detecting portion 30 detecting that the voltage values of control terminals of the output switching elements M1 and M2 have exceeded the threshold voltage value; an auxiliary driving portion 40 being connected to the driving portion 20 and changing driving capability of the output switching elements M1 and M2 in accordance with the result of detection by the detecting portion 30.
摘要翻译：已经公开了本公开，以提供一种缓冲电路及其控制方法，其能够控制输出开关元件从OFF状态变为ON状态的定时，并且防止输出特性变得不稳定。缓冲电路包括：驱动输出开关元件M1和M2的驱动部分20; 检测部分30，检测输出开关元件M1和M2的控制端的电压值已经超过阈值电压值; 辅助驱动部分40连接到驱动部分20，并且根据检测部分30的检测结果改变输出开关元件M1和M2的驱动能力。

40. 发明授权

US07880521B2 Differential driver and method capable of controlling slew rate 有权
标题翻译：差分驱动器和方法能够控制转换速率
公开(公告)号：US07880521B2
公开(公告)日：2011-02-01
申请号：US11882567
申请日：2007-08-02
申请人： Hitoshi Okamura , Byung-Hyun Lim
发明人： Hitoshi Okamura , Byung-Hyun Lim
IPC分类号： H03K5/12
CPC分类号： H03K5/12
摘要： A differential driver includes first and second pull-up resistors respectively connected to first and second output terminals, a plurality of differential-input transistor pairs connected each to the first and second output terminals, current sources connected each to the differential-input transistor pairs, and a slew rate controller adapted to generate differential input signals to be applied each to the differential-input transistor pairs in response to an input signal. The slew rate controller may output the differential input signals simultaneously or sequentially.
摘要翻译：差分驱动器包括分别连接到第一和第二输出端子的第一和第二上拉电阻器，每个连接到第一和第二输出端子的多个差分输入晶体管对，每个连接到差分输入晶体管对的电流源，以及转换速率控制器，其适于响应于输入信号产生要分别施加到差分输入晶体管对的差分输入信号。转换速率控制器可以同时或顺序地输出差分输入信号。

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