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1. 发明授权

US06940305B2 Low leakage Ioff and overvoltage Ioz circuit 有权
标题翻译：低泄漏Ioff和过电压Ioz电路
公开(公告)号：US06940305B2
公开(公告)日：2005-09-06
申请号：US10704410
申请日：2003-11-07
申请人： Mark B. Welty
发明人： Mark B. Welty
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/00315
摘要： A blocking circuit technique achieves very low Ioff and Ioz leakage in low power digital logic devices that incorporate Ioff and overvoltage tolerance. The blocking circuit employs a diode-connected P-channel device in parallel with a PN diode. The diode-connected P-channel device provides enough forward leakage in the subthreshold region to keep Ioz through the upper output driver to a very low level (0.2 uA typical). Further, both the diode-connected P-channel device and the PN diode together provide enough reverse blocking capability to keep Ioff to a very low level (0.2 uA typical).
摘要翻译：阻塞电路技术在低功耗数字逻辑器件中实现非常低的Ioff和Ioz泄漏，其包含Ioff和过压容限。阻塞电路使用与PN二极管并联的二极管连接的P沟道器件。二极管连接的P沟道器件在亚阈值区域提供足够的正向泄漏，以将Ioz通过上部输出驱动器保持在非常低的电平（典型值为0.2 uA）。此外，二极管连接的P沟道器件和PN二极管一起提供足够的反向阻断能力，以将Ioff保持在非常低的电平（典型值为0.2 uA）。

2. 发明授权

US08040171B2 Accelerator output stage that adjusts drive duration to loading 有权
标题翻译：加速器输出级，可调整驱动持续时间加载
公开(公告)号：US08040171B2
公开(公告)日：2011-10-18
申请号：US11382995
申请日：2006-05-12
申请人： Mark B. Welty
发明人： Mark B. Welty
IPC分类号： H03K5/12
CPC分类号： H03K5/12 , H03K17/04206 , H03K17/6872 , H03K19/0016 , H03K19/00361
摘要： The accelerator output stage circuit includes: a high side output device coupled to an output node; a low side output device coupled to the output node; a first logic gate coupled to a control node of the first high side output device; a second logic gate coupled to a control node of the second high side output device; a high side one-shot device having an output coupled to a first input of the first logic gate; a low side one-shot device having an output coupled to a first input of the second logic gate; and a feedback device coupled between the output node and a second input of the first logic gate, and between the output node and a second input of the second logic gate, and between the output node and the input to the high side resistor bypass device, and between the output node and the input to the low side one-shot resistor bypass device.
摘要翻译：加速器输出级电路包括：耦合到输出节点的高侧输出装置; 耦合到所述输出节点的低侧输出装置; 耦合到所述第一高侧输出装置的控制节点的第一逻辑门; 耦合到所述第二高侧输出装置的控制节点的第二逻辑门; 具有耦合到第一逻辑门的第一输入的输出的高边单触发器件; 具有耦合到第二逻辑门的第一输入的输出的低侧单触发器件; 以及耦合在所述输出节点和所述第一逻辑门的第二输入之间以及所述输出节点和所述第二逻辑门的第二输入之间以及所述输出节点与所述高侧电阻器旁路装置的输入之间的反馈装置，并在输出节点和低端单稳态电阻旁路装置的输入之间。

3. 发明授权

US07282964B2 Circuit for detecting transitions on either of two signal lines referenced at different power supply levels 有权
标题翻译：用于检测在不同电源电平上引用的两条信号线之一上的转换的电路
公开(公告)号：US07282964B2
公开(公告)日：2007-10-16
申请号：US11239194
申请日：2005-09-29
申请人： Mark B. Welty
发明人： Mark B. Welty
IPC分类号： H03K5/22 , H03K19/0175
CPC分类号： H03K5/1534
摘要： A transition detect circuit includes: a first input port referenced to a first supply voltage node and a second input port referenced to a second supply voltage node. The circuit simultaneously monitors both ports for transitions, and once a transition occurs, directly generates the translated control signals at its output. Once a transition occurs at the inputs, the translated control signal is generated at the output within at most two gate delays. The circuit has very low quiescent current.
摘要翻译：转换检测电路包括：参考第一电源电压节点的第一输入端口和参考第二电源电压节点的第二输入端口。电路同时监控两个端口的转换，一旦发生转换，就会在其输出端直接产生转换后的控制信号。一旦在输入端发生转换，则转换的控制信号在最多两个门延迟的输出处产生。该电路具有非常低的静态电流。

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