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31. 发明授权

US08119497B2 Thin embedded active IC circuit integration techniques for flexible and rigid circuits 失效
标题翻译：薄型嵌入式有源IC电路集成技术，用于柔性和刚性电路
公开(公告)号：US08119497B2
公开(公告)日：2012-02-21
申请号：US11981017
申请日：2007-10-31
申请人： Glenn Alan Forman , Kelvin Ma
发明人： Glenn Alan Forman , Kelvin Ma
IPC分类号： H01L21/30
CPC分类号： H01L23/5389 , H01L21/6835 , H01L23/48 , H01L23/5387 , H01L23/552 , H01L23/66 , H01L24/24 , H01L24/82 , H01L2221/6834 , H01L2221/68363 , H01L2224/24137 , H01L2224/24226 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H05K1/185 , H05K1/189 , H05K3/4614 , H05K3/4617
摘要： A flexible electronic circuit member formed of a plurality of dielectric layers includes a plurality of thinned semiconductor chips embedded within the circuit member for increased levels of integration and component density. The thinned semiconductor chips may include various integrated circuits thereon. They may be formed on various substrates and using various technologies and the embedded, thinned semiconductor chips are interconnected by a patterned interconnect that extends between and through the respective dielectric layers. A method for forming the flexible circuit member includes joining semiconductor chips to a mounting apparatus using a releasable bonding layer then forming thinned semiconductor chips that are joined to respective dielectric layers that combine to form the flexible electronic circuit member. The releasable bonding layer is removed after the thinned semiconductor chips are joined to the respective dielectric layers used in combination to form the electronic circuit member.
摘要翻译：由多个电介质层形成的柔性电子电路部件包括嵌入电路部件内的多个变薄的半导体芯片，用于提高集成度和部件密度。减薄的半导体芯片可以包括其上的各种集成电路。它们可以形成在各种基板上并使用各种技术，并且嵌入的，变薄的半导体芯片通过在相应的电介质层之间延伸并穿过各个电介质层的图案化互连而互连。形成柔性电路部件的方法包括：使用可剥离接合层将半导体芯片接合到安装装置，然后形成连接到组合形成柔性电子电路部件的各个电介质层的变薄的半导体芯片。在将薄化的半导体芯片组合到组合使用的各个电介质层之后，去除可剥离接合层，以形成电子电路部件。

32. 发明授权

US08106306B2 Ceramic multi-layer circuit substrate and manufacturing method thereof 有权
标题翻译：陶瓷多层电路基板及其制造方法
公开(公告)号：US08106306B2
公开(公告)日：2012-01-31
申请号：US12405729
申请日：2009-03-17
申请人： Won Hee Yoo , Byeung Gyu Chang , Taek Jung Lee , Yong Suk Kim
发明人： Won Hee Yoo , Byeung Gyu Chang , Taek Jung Lee , Yong Suk Kim
IPC分类号： H05K1/00
CPC分类号： H05K3/4629 , B32B18/00 , C04B37/005 , C04B2237/04 , C04B2237/32 , C04B2237/52 , C04B2237/562 , C04B2237/565 , C04B2237/595 , C04B2237/62 , C04B2237/68 , C04B2237/704 , C04B2237/708 , H05K1/0306 , H05K3/1291 , H05K3/4617 , H05K2201/0195 , H05K2201/096 , H05K2201/10378 , H05K2203/1126 , H05K2203/1476
摘要： Provided is a method of manufacturing a ceramic multi-layer circuit substrate. A plurality of ceramic blocks, in each of which one or more ceramic green sheets having via-electrodes are layered one atop the other, are formed and are then fired. The fired ceramic blocks are aligned with each other. One or more bonding green sheets each having bonding electrodes in positions corresponding to the via-electrodes of the ceramic blocks are prepared. Each of the bonding green sheets is interposed between a pair of the ceramic blocks opposing each other. The ceramic blocks and the bonding green sheets are bonded and are then fired.
摘要翻译：提供一种制造陶瓷多层电路基板的方法。形成多个陶瓷块，每个陶瓷块中的一个或多个具有通孔电极的陶瓷生片分别彼此层叠，然后烧制。烧制的陶瓷块彼此对准。制备一个或多个接合生片，每个接合生片具有与陶瓷块的通孔电极对应的位置的接合电极。每个接合生片被插入在彼此相对的一对陶瓷块之间。陶瓷块和接合生片结合，然后烧制。

33. 发明申请

US20120000695A1 RESIN CIRCUIT BOARD 有权
标题翻译：树脂电路板
公开(公告)号：US20120000695A1
公开(公告)日：2012-01-05
申请号：US13227523
申请日：2011-09-08
申请人： Shunsuke CHISAKA
发明人： Shunsuke CHISAKA
IPC分类号： H05K1/02
CPC分类号： H05K1/0271 , H05K1/09 , H05K3/4617 , H05K3/4632 , H05K2201/0338 , H05K2201/068
摘要： A resin circuit board includes a layered structure of resin layers and conductor layers, has significantly reduced and minimized warping and distortion, and has a precise shape. A second conductor layer is disposed between a resin layer and a first conductor layer made of a metal. The resin layer and the second conductor layer have a higher thermal expansion coefficient than the first conductor layer such that the thermal expansion coefficient changes gradually, allowing a stress resulting from a difference in thermal expansion coefficient to be relieved.
摘要翻译：树脂电路板包括树脂层和导体层的层状结构，具有显着减小并且最小化翘曲和变形，并且具有精确的形状。第二导体层设置在树脂层和由金属制成的第一导体层之间。树脂层和第二导体层具有比第一导体层更高的热膨胀系数，使得热膨胀系数逐渐变化，从而可以减轻由热膨胀系数的差引起的应力。

34. 发明申请

US20110042124A1 MULTILAYER WIRING SUBSTRATE HAVING CAVITY PORTION 审中-公开
标题翻译：具有空腔部分的多层接线基板
公开(公告)号：US20110042124A1
公开(公告)日：2011-02-24
申请号：US12745651
申请日：2008-12-03
申请人： Jun Matsui , Shingetsu Yamada
发明人： Jun Matsui , Shingetsu Yamada
IPC分类号： H01B17/00 , H05K1/00 , H05K3/06 , H05K3/00
CPC分类号： H05K1/183 , H01L33/486 , H01L2224/32013 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/49107 , H01L2224/73265 , H01L2924/12044 , H05K1/0274 , H05K1/0373 , H05K3/4617 , H05K3/4632 , H05K3/4688 , H05K3/4697 , H05K2201/0129 , H05K2201/0209 , H05K2201/10106 , H05K2201/2054 , H05K2203/063 , H01L2924/00014 , H01L2924/00
摘要： The present invention provides a multilayer wiring substrate comprising: a plurality of wiring substrate laminated each other; and a cavity portion. In the multilayer wiring substrate, a wiring substrate 1 being arranged along the bottom face of the cavity portion and a wiring substrate 2 being arranged at an upper layer side of the wiring substrate 1, the wiring substrate 1 and/or the wiring substrate 2 respectively comprising an insulating base material having a predetermined properties, the wiring substrate 2 being provided with a cavity hole. Thus, it is possible to provide a multilayer wiring substrate having a cavity portion and even a function of reflector.
摘要翻译：本发明提供一种多层布线基板，包括：多个彼此层叠的布线基板; 和空腔部分。在多层布线基板中，布线基板1沿着空腔部的底面配置，布线基板2分别配置在布线基板1，布线基板1和/或布线基板2的上层侧包括具有预定特性的绝缘基材，所述布线基板2设置有空腔孔。因此，可以提供具有空腔部分和甚至反射器功能的多层布线基板。

35. 发明授权

US07889510B2 Component-embedded board device and faulty wiring detecting method for the same 有权
标题翻译：组件嵌入式电路板设备和故障接线检测方法相同
公开(公告)号：US07889510B2
公开(公告)日：2011-02-15
申请号：US11797206
申请日：2007-05-01
申请人： Satoshi Takeuchi , Hiroki Kamiya , Katsunori Kubota , Motoki Shimizu
发明人： Satoshi Takeuchi , Hiroki Kamiya , Katsunori Kubota , Motoki Shimizu
IPC分类号： H05K1/18
CPC分类号： G01R31/2818 , G01R31/2812 , H05K1/0268 , H05K1/186 , H05K3/4614 , H05K3/4617 , H05K2201/0394 , H05K2201/09254 , H05K2201/10636 , H05K2203/063 , Y02P70/611
摘要： A component-embedded board device has a wiring board in which an electronic component is embedded, a connection member which is conductive and arranged at a surface of the wiring board, and an inner wiring unit which is arranged in the wiring board and connects an electrode of the electronic component with the connection member. The component-embedded board device is further provided with an inspection connection member for an inspection of a faulty wiring of the inner wiring unit, and an inspection wiring unit which is arranged in the wiring board and connects the inspection connection member with one of the electrode and a predetermined portion of the inner wiring unit. The inspection connection member is conductive and arranged at a surface of the wiring board.
摘要翻译：组件嵌入式板装置具有嵌入有电子部件的布线基板，导电性配置在配线基板的表面的连接部件和配置在配线基板上的内部配线部，的电子部件。组件嵌入式板装置还具有用于检查内部布线单元的故障布线的检查连接构件和布置在布线板中并将检查连接构件与电极之一连接的检查布线单元和内部布线单元的预定部分。检查连接构件是导电的并且布置在布线板的表面上。

36. 发明授权

US07856706B2 Methods of manufacturing printed circuit boards with stacked micro vias 有权
标题翻译：制造具有堆叠微通孔的印刷电路板的方法
公开(公告)号：US07856706B2
公开(公告)日：2010-12-28
申请号：US12381925
申请日：2009-03-17
申请人： Raj Kumar , Monte Dreyer , Michael J. Taylor
发明人： Raj Kumar , Monte Dreyer , Michael J. Taylor
IPC分类号： H05K3/36
CPC分类号： H05K3/4623 , H05K3/205 , H05K3/386 , H05K3/4069 , H05K3/423 , H05K3/4614 , H05K3/4617 , H05K3/462 , H05K2201/0355 , H05K2201/0394 , H05K2201/09309 , H05K2201/096 , H05K2203/0191 , H05K2203/0271 , H05K2203/0502 , H05K2203/061 , H05K2203/0733 , H05K2203/107 , H05K2203/1461 , H05K2203/1536 , H05K2203/304 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A method of manufacturing at least a portion of a printed circuit board. The method includes: applying a lamination adhesive on a first plural-layer substrate that includes a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate; applying a protective film on the lamination adhesive; forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate; filling at least one conductive paste into the at least one via formed in the lamination adhesive; removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and attaching the first plural-layer substrate with a second plural-layer substrate that includes a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate.
摘要翻译：一种制造印刷电路板的至少一部分的方法。该方法包括：在第一多层基板上施加层压粘合剂，该第一多层基板包括多个电路层，在第一多层基板的第一侧具有至少一个第一金属焊盘; 在层压粘合剂上涂上保护膜; 将至少一个通孔形成到所述层压粘合剂中以暴露所述第一多层基板的第一侧上的所述至少一个金属焊盘; 将至少一个导电浆料填充到在层压粘合剂中形成的至少一个通孔中; 去除所述保护膜以将所述层叠粘合剂暴露在所述第一多层基板上; 以及在所述第二多层基板的第二面上，将具有包含多个电路层的第二多层基板与至少一个第二金属焊盘连接的第一多层基板。

37. 发明申请

US20100276184A1 MULTILAYER PRINTED BOARD AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：多层印刷板及其制造方法
公开(公告)号：US20100276184A1
公开(公告)日：2010-11-04
申请号：US12810522
申请日：2008-12-19
申请人： Satoru Zama , Kenichi Ohga , Akira Tachibana
发明人： Satoru Zama , Kenichi Ohga , Akira Tachibana
IPC分类号： H05K1/14 , B32B37/00 , H05K1/03 , H05K1/09
CPC分类号： H05K3/4614 , H05K3/281 , H05K3/426 , H05K3/4617 , H05K3/462 , H05K3/4632 , H05K2201/0129 , H05K2201/035 , H05K2201/09563 , H05K2201/096 , H05K2203/063 , Y10T156/10
摘要： Provided is a multilayer printed board 10 having three single-sided conductor pattern films 16 each having a conductor pattern 13 formed on one surface of a resin film 12 having a through hole 11 and a filled through hole 15 that is the through hole 11 filled with a conductor 14 integrally with the conductor pattern 13. These single-sided conductor pattern films 16 are stacked in such a manner that their tops are oriented in the same way. The conductor patterns 13 of the single-sided conductor pattern films 16 are electrically connected via the filled through holes 15. As the conductor patterns 13 of the single-sided conductor pattern films 16 are interlayer connected via the filled through holes 15, the interlayer connection reliability can be enhanced.
摘要翻译：提供了具有三个单面导体图案膜16的多层印刷电路板10，每个单面导体图案膜16具有形成在具有通孔11的树脂膜12的一个表面上的导体图案13和填充有通孔11的填充通孔15，与导体图案13一体地形成的导体14.这些单面导体图案膜16以它们的顶部以相同的方式定向的方式堆叠。单面导体图案膜16的导体图案13经由填充的通孔15电连接。当单面导体图案膜16的导体图案13经由填充的通孔15层间连接时，层间连接可靠性可以提高。

38. 发明申请

US20100212937A1 PROCESS FOR MANUFACTURING CIRCUIT BOARD AND CIRCUIT BOARD 失效
标题翻译：制造电路板和电路板的过程
公开(公告)号：US20100212937A1
公开(公告)日：2010-08-26
申请号：US12160718
申请日：2006-02-13
申请人： Masayoshi Kondo , Toshio Komiyatani
发明人： Masayoshi Kondo , Toshio Komiyatani
IPC分类号： H05K1/00 , H05K13/00
CPC分类号： H05K3/4617 , H05K3/3489 , H05K3/386 , H05K3/423 , H05K2201/0195 , H05K2201/0394 , H05K2203/068 , H05K2203/0733 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49156 , Y10T29/49165
摘要： According to the present invention, there is provided a process for manufacturing a circuit board wherein a first substrate having a conductor post and a second substrate having a conductor pad for receiving the conductor post are laminated through an interlayer adhesive, and the conductor post and the conductor pad are electrically connected, comprising, as a first step, bonding the conductor pad with the conductor post by thermocompression under predetermined first conditions while the first and the second substrates are arranged such that the conductor pad faces the conductor post through the interlayer adhesive; thermocompressing the first substrate and the second substrate under predetermined second conditions while the conductor pad is bonded with the conductor post; and thermocompressing the first substrate and the second substrate under predetermined third conditions while the conductor pad is bonded with the conductor post, wherein the first, the second and the third conditions are different from each other.
摘要翻译：根据本发明，提供了一种制造电路板的方法，其中具有导体柱的第一基板和具有用于接纳导体柱的导体焊盘的第二基板通过层间粘合剂层压，并且导体柱和电导体焊盘电连接，包括作为第一步骤，在预定的第一条件下通过热压接将导体焊盘与导体柱接合，同时布置第一和第二基板，使得导体焊盘通过层间粘合剂面对导体柱; 在导体焊盘与导体柱接合的同时，在预定的第二条件下热压第一衬底和第二衬底; 以及在所述导体焊盘与所述导体柱接合的同时在预定的第三条件下热压所述第一基板和所述第二基板，其中所述第一，第二和第三条件彼此不同。

39. 发明授权

US07750650B2 Solid high aspect ratio via hole used for burn-in boards, wafer sort probe cards, and package test load boards with electronic circuitry 失效
标题翻译：用于老化板，晶圆分选探针卡和带电子电路的封装测试负载板的固体高纵横比通孔
公开(公告)号：US07750650B2
公开(公告)日：2010-07-06
申请号：US11685866
申请日：2007-03-14
申请人： Romi O. Mayder
发明人： Romi O. Mayder
IPC分类号： G01R1/02 , H01R12/04
CPC分类号： H05K3/4617 , G01R31/2863 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L2224/16227 , H01L2224/16235 , H01L2924/0002 , H01L2924/15311 , H05K1/0206 , H05K1/113 , H05K3/0047 , H05K3/0094 , H05K3/4061 , H05K3/4611 , H05K3/4679 , H05K2201/096 , H05K2203/0733 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165 , Y10T29/49172 , H01L2924/00
摘要： A method, and apparatus resulting from the method, for fabricating a circuit board suitable for mounting electronic components. The method includes drilling a plurality of through-holes in a plurality of dielectric sheets, forming a conductive film on at least one side of each of the plurality of dielectric sheets, and substantially filling each of the plurality of through holes with a conductive material. The conductive material is both electrically and thermally uninterrupted from a first face to a second face of each of the plurality of dielectric sheets. The plurality of dielectric sheets are then sequentially mounted, on atop another, to form the circuit board. The sequential mounting step is performed after the steps of drilling the plurality of through-holes, forming the conductive layer, and substantially filling the plurality of through-holes.
摘要翻译：一种用于制造适于安装电子部件的电路板的由该方法得到的方法和装置。该方法包括在多个电介质片中钻出多个通孔，在多个电介质片的每一个的至少一侧上形成导电膜，并且用导电材料基本上填充多个通孔中的每一个。导电材料从多个电介质片的每一个的第一面到第二面都是电而且不间断的。然后将多个电介质片依次安装在另一个上，形成电路板。在钻出多个通孔，形成导电层并基本上填充多个通孔的步骤之后执行顺序安装步骤。

40. 发明授权

US07733665B2 Multi-layer substrate having conductive pattern and resin film and method for manufacturing the same 有权
标题翻译：具有导电图案的多层基板和树脂膜及其制造方法
公开(公告)号：US07733665B2
公开(公告)日：2010-06-08
申请号：US11431572
申请日：2006-05-11
申请人： Toshikazu Harada , Kouji Kondo
发明人： Toshikazu Harada , Kouji Kondo
IPC分类号： H05K1/11
CPC分类号： H05K3/4688 , H01L2924/0002 , H05K1/0237 , H05K1/0265 , H05K1/036 , H05K3/382 , H05K3/4617 , H05K3/4632 , H05K2201/0129 , H05K2201/0195 , H05K2201/0352 , H05K2201/09736 , H01L2924/00
摘要： A multi-layer substrate connecting to an external electric device includes: a plurality of resin films; and a plurality of conductive patterns. The resin films are stacked together with the conductive patterns. The conductive pattern includes an inner conductive pattern and a surface conductive pattern. The inner conductive pattern is disposed inside of the multi-layer substrate for providing an inner circuit. The surface conductive pattern is exposed on the multi-layer substrate for connecting to the external electric device. The surface conductive pattern has a thickness in a stacking direction, which is thicker than a thickness of the inner conductive pattern.
摘要翻译：连接到外部电气装置的多层基板包括：多个树脂膜; 和多个导电图案。树脂膜与导电图案堆叠在一起。导电图案包括内导电图案和表面导电图案。内部导电图案设置在多层基板的内部，用于提供内部电路。表面导电图案暴露在多层基板上，用于连接外部电气装置。表面导电图案的层叠方向的厚度比内部导电图案的厚度厚。

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