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31. 发明授权

US3677759A Photographically producing molecularly dispersed dye images 失效
标题翻译：摄影制作分子染色体图像
公开(公告)号：US3677759A
公开(公告)日：1972-07-18
申请号：US3677759D
申请日：1969-06-16
申请人： STALEY MFG CO A E
发明人： JONES REXFORD W , THOMPSON WILLIAM B
IPC分类号： B41M5/00 , G03G7/00 , G03G11/00 , G03C1/68 , G03C5/24
CPC分类号： G03G7/00 , B41M5/0029 , G03G11/00 , H05K2203/0525 , H05K2203/0585 , H05K2203/1355
摘要： PROCESS OF MOLECULARLY DISPERISING PARTICULATE DYE IMAGES WHEREIN POWDER PARTICLES COMPRISING A CARRIER AND A DYE, HELD IN IMAGEWISE CONFIGURATION IN PARTICULATE FORM IN OR ON A SUBSTRATE, ARE CONTACTED WITH VAPORS OF A MATERIAL, WHICH IS A SOLVENT FOR SAID DYE, CAPABLE OF SWELLING SAID CARRIER AND INCAPABLE OF SWELLING THE SURFACE OF SAID SUBSTRATE, MOLECULARLY DISPERSING SAID DYE IN SAID CARRIER. LINE, CONTINUOUS-TONER OR HALF-TONE IMAGES ARE PREFERABLY PRODUCED BY EXPOSING TO ACTINIC RADIATION IN IMAGE-RECEIVING MANNER A SUBSTRATE BEARING A POSITIVE-ACTING OR NEGATIVE-ACTING LIGHT-SENSITIVE ORGANIC LAYER HAVING A THICKNESS OF AT LEAST 0.1 MICRON, SAID LAYER BEING CAPABLE OF DEVELOPING A RD OF 0.2 TO 2.2; CONTINUING THE EXPOSURE TO EITHER CLEAR THE BACKGROUND OF POSITIVE-ACTING LIGHTSENSITIVE LAYERS OR TO ESTABLISH A POTENTIAL RD OF 0.2 TO 2.2 WITH NEGATIVE-ACTING LIGHT-SENSITIVE ORGANIC LAYER; APPLYING TO SAID LAYER OF ORGANIC MATERIAL, FREE FLOWING POWDER PARTICLES HAVING A DIAMETER, ALONG AT LEAST ONE AXIS OF AT LEAST ABOUT 0.3 MICRON BUT LESS THAN 25 TIMES THE THICKNESS OF SAID ORGANIC LAYER WHEREIN SAID POWDER PARTICLES COMPRISE A SOLID CARRIER AND DYE; WHILE THE LAYER IS AT A TEMPERATURE BELOW THE MELTING POINTS OF THE POWDER AND OF THE ORGANIC LAYER, PHYSICALLY EMEDDING SAID POWDER PARTICLES AS A MONOLAYER IN A STRATUM AT THE SURFACE OF SAID LIGHT-SENSITIVE LAYER TO YIELD IMAGES HAVING PORTIONS VARYING IN DENSITY IN PROPORTION TO THE LIGHT EXPOSURE OF EACH PORTION, REMOVING NON-EMBEDDED PARTICLES FROM SAID ORGANIC LAYER TO DEVELOP AN IMAGE; AND MOLECULARLY DISPERSING DYE INTO SAID CARRIER BY CONTACTING THE PARTICLES EMBEDDED IN SAID ORGANIC LAYER WITH VAPORS OF A MATERIAL WHICH IS A SOLVENT FOR SAID DYE, CAPABLE OF SWELLING SAID CARRIER AND INCAPABLE OF SWELLING THE SURFACE OF SAID SUBSTRATE.

32. 发明授权

US07569333B2 Wiring line structure and method for forming the same 有权
标题翻译：接线结构及其形成方法
公开(公告)号：US07569333B2
公开(公告)日：2009-08-04
申请号：US11852365
申请日：2007-09-10
申请人： Tzeng-Guang Tsai , Kuo-Yu Huang , Hui-Fen Lin , Yu-Wei Liu
发明人： Tzeng-Guang Tsai , Kuo-Yu Huang , Hui-Fen Lin , Yu-Wei Liu
IPC分类号： G03F7/00 , G03C5/00 , C23C28/00
CPC分类号： H01L21/76885 , G02F2001/136295 , H01L21/76834 , H05K3/0023 , H05K3/064 , H05K3/108 , H05K3/388 , H05K2201/0108 , H05K2203/0571 , H05K2203/0585 , H05K2203/0597
摘要： The wiring line structure comprises a transparent substrate, a barrier layer, a metal layer, and a photosensitive protecting layer. The barrier layer and a metal layer are successively disposed on the transparent substrate. The photosensitive protecting layer is formed on the barrier layer and both sides of the metal layer. A method for fabricating the wiring line structure is also disclosed.
摘要翻译：布线线结构包括透明基板，阻挡层，金属层和光敏保护层。阻挡层和金属层依次设置在透明基板上。感光保护层形成在阻挡层和金属层的两侧。还公开了一种用于制造布线结构的方法。

33. 发明申请

US20090184413A1 INSULATIVE WIRING BOARD, SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD FOR PRODUCING THE INSULATIVE WIRING BOARD 审中-公开
标题翻译：绝缘导线板，使用其的半导体封装以及用于制造绝缘导线板的方法
公开(公告)号：US20090184413A1
公开(公告)日：2009-07-23
申请号：US12212089
申请日：2008-09-17
申请人： Kazuaki TATSUMI , Yoshiki SOTA
发明人： Kazuaki TATSUMI , Yoshiki SOTA
IPC分类号： H01L23/498 , H05K1/05 , H01L21/50
CPC分类号： H05K3/3452 , H01L23/49827 , H01L23/49838 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32057 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/15151 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/20752 , H01L2924/3511 , H05K1/112 , H05K3/0094 , H05K3/427 , H05K2201/0959 , H05K2201/0989 , H05K2201/10734 , H05K2203/0585 , H05K2203/1178 , H01L2924/00014 , H01L2924/3512 , H01L2924/00 , H01L2924/00012
摘要： The insulative wiring board of the present invention, with its both surfaces being covered with solder resist, includes at least one via hole in a semiconductor chip-mounting area penetrating the insulative wiring board, wherein conductor layers are electrically connected to each other via said at least one via hole. Further, the mounting area is covered with the solder resist, excluding said at least one via hole that penetrates the insulative wiring board. Therefore, it is possible to achieve an insulative wiring board that prevents defects caused by expansion occurred due to heating of moisture absorbed by the board, as well as reducing an area where a wiring cannot be provided.
摘要翻译：本发明的绝缘布线基板，其两面被阻焊剂覆盖，包括穿过绝缘布线板的半导体芯片安装区域中的至少一个通路孔，其中导体层经由所述导电层彼此电连接至少一个通孔。此外，除了穿过绝缘布线板的所述至少一个通孔之外，用阻焊剂覆盖安装区域。因此，可以实现防止由于板吸收的水分的加热而发生的膨胀引起的缺陷的绝缘布线板以及减少不能提供布线的区域。

34. 发明授权

US07524764B2 Method of forming film pattern, device, method of manufacturing the same, electro-optical apparatus, and electronic apparatus 失效
标题翻译：形成膜图案的方法，装置，制造方法，电光装置和电子设备
公开(公告)号：US07524764B2
公开(公告)日：2009-04-28
申请号：US11326914
申请日：2006-01-06
申请人： Toshimitsu Hirai
发明人： Toshimitsu Hirai
IPC分类号： H01L21/44
CPC分类号： H05K3/1258 , H01L27/14601 , H01L51/0005 , H05K3/125 , H05K2201/0175 , H05K2203/013 , H05K2203/0585
摘要： A method of forming a film pattern by disposing a functional liquid on a substrate, includes: forming banks on the substrate; disposing the functional liquid in areas partitioned by the banks; and drying the functional liquid disposed on the substrate, wherein the forming of the banks including: forming a plurality of layers made of inorganic materials; patterning a plurality of the layers by using an organic mask; and removing the organic mask.
摘要翻译：通过在基板上设置功能液来形成膜图案的方法包括：在基板上形成堤; 将功能液体置于由银行划分的区域内; 以及干燥设置在所述基板上的功能性液体，其中所述堤的形成包括：形成由无机材料制成的多个层; 通过使用有机掩模来图案化多个层; 并去除有机掩模。

35. 发明申请

US20070187136A1 Printed circuit board, method of producing the same, and electronic unit 审中-公开
标题翻译：印刷电路板，其制造方法和电子单元
公开(公告)号：US20070187136A1
公开(公告)日：2007-08-16
申请号：US11230965
申请日：2005-09-20
申请人： Masahiro Higashiguchi , Kunihiro Tan
发明人： Masahiro Higashiguchi , Kunihiro Tan
IPC分类号： H05K1/00
CPC分类号： H05K3/284 , H01L23/24 , H01L2224/48091 , H01L2224/73265 , H01L2924/3025 , H05K2203/0585 , H05K2203/0588 , H05K2203/0594 , H01L2924/00014 , H01L2924/00
摘要： A printed circuit board is disclosed that is able to prevent outflow of a potting resin out of a sealing region. The printed circuit board includes a conductive pattern formed on an insulating substrate, an electrode for connecting an electronic part to the conductive pattern, and a stripe-like resin-outflow-prevention dam arranged in a periphery of a resin-sealing region covering the electronic part. An outer side surface and an upper surface of the resin-outflow-prevention dam subtend an acute angle.
摘要翻译：公开了能够防止灌封树脂从密封区域外流出的印刷电路板。印刷电路板包括形成在绝缘基板上的导电图案，用于将电子部件连接到导电图案的电极和布置在覆盖电子部件的树脂密封区域的周围的条状树脂流出防止坝部分。树脂流出防止坝的外侧表面和上表面对准锐角。

36. 发明申请

US20060177951A1 Method of forming film pattern, device, method of manufacturing the same, electro-optical apparatus, and electronic apparatus 失效
公开(公告)号：US20060177951A1
公开(公告)日：2006-08-10
申请号：US11326914
申请日：2006-01-06
申请人： Toshimitsu Hirai
发明人： Toshimitsu Hirai
IPC分类号： H01L21/00
CPC分类号： H05K3/1258 , H01L27/14601 , H01L51/0005 , H05K3/125 , H05K2201/0175 , H05K2203/013 , H05K2203/0585
摘要： A method of forming a film pattern by disposing a functional liquid on a substrate, includes: forming banks on the substrate; disposing the functional liquid in areas partitioned by the banks; and drying the functional liquid disposed on the substrate, wherein the forming of the banks including: forming a plurality of layers made of inorganic materials; patterning a plurality of the layers by using an organic mask; and removing the organic mask.

37. 发明申请

US20030080420A1 Semiconductor chip and wiring board and manufacturing method of the same, semiconductor wafer, semiconductor device, circuit board, and electronic instrument 失效
标题翻译：半导体芯片和布线板及其制造方法，半导体晶片，半导体器件，电路板和电子仪器
公开(公告)号：US20030080420A1
公开(公告)日：2003-05-01
申请号：US10277114
申请日：2002-10-22
申请人： SEIKO EPSON CORPORATION
发明人： Hiroshi Ohara
IPC分类号： H01L021/44 , H01L023/48 , H01L029/40
CPC分类号： H01L24/12 , H01L23/3171 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/02166 , H01L2224/0401 , H01L2224/05567 , H01L2224/1147 , H01L2224/11472 , H01L2224/13099 , H01L2224/13147 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/19043 , H05K3/28 , H05K3/4007 , H05K2201/0367 , H05K2203/0585 , H05K2203/072 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
摘要： An integrated circuit is electrically connected with a plurality of pads. A passivation film covers a part of each of the pads and exposes the other part of each of the pads. Bumps are formed on the pads, respectively. Each of the bumps is a single layer disposed on a part of each of the pads exposed from the passivation film, and on the passivation film.
摘要翻译：集成电路与多个焊盘电连接。钝化膜覆盖每个焊盘的一部分并且暴露每个焊盘的另一部分。分别在焊盘上形成凸起。每个凸起是设置在从钝化膜暴露的每个焊盘的一部分上以及钝化膜上的单层。

38. 发明授权

US6165892A Method of planarizing thin film layers deposited over a common circuit base 失效
标题翻译：在公共电路基底上沉积薄膜层的平面化方法
公开(公告)号：US6165892A
公开(公告)日：2000-12-26
申请号：US127580
申请日：1998-07-31
申请人： David J. Chazan , Ted T. Chen , Todd S. Kaplan , James L. Lykins , Michael P. Skinner , Jan I. Strandberg
发明人： David J. Chazan , Ted T. Chen , Todd S. Kaplan , James L. Lykins , Michael P. Skinner , Jan I. Strandberg
IPC分类号： H01L21/48 , H01L23/538 , H05K1/02 , H05K3/00 , H05K3/46 , H01L21/4763
CPC分类号： H05K3/4673 , H01L21/481 , H01L21/4857 , H01L23/5383 , H01L23/5385 , H01L2924/0002 , H01L2924/3011 , H05K1/0271 , H05K3/0023 , H05K3/0032 , H05K3/4602 , H05K3/4644 , H05K2201/0195 , H05K2201/068 , H05K2201/09536 , H05K2201/0959 , H05K2201/09881 , H05K2203/0585 , H05K2203/0759 , H05K2203/1476 , H01L2924/00
摘要： A method for forming a planarized thin film dielectric film on a surface of a common circuit base upon which one or more integrated circuits are to be attached. The common circuit base includes raised features formed over its surface such that the raised features define a trench area between them. The method includes the steps of forming a first layer of the dielectric film over the common circuit base and over the raised features and the trench, then patterning the newly formed layer to remove portions of the layer formed over the raised features and expose the raised features. After the layer is patterned, formation of the dielectric film is completed by forming a second layer of the dielectric film over the patterned first layer. Additional film deposition and film patterning steps are performed to complete the layout of a thin film interconnect structure over said common circuit base, and an integrated circuit die is attached to the common circuit base and electrically connecting to the thin film interconnect structure. In a preferred embodiment, the first and second layers of the dielectric film are both formed from a photo-definable material and the patterning step includes exposing the first layer to light through a patterned mask corresponding to the raised features and developing the exposed layer with a developing solution to etch away portions of the first layer formed over the raised features.
摘要翻译：一种用于在公共电路基底的表面上形成平坦化的薄膜电介质膜的方法，一个或多个集成电路将安装在该公共电路基底上。公共电路基座包括在其表面上形成的凸起特征，使得凸起特征在它们之间限定沟槽区域。该方法包括以下步骤：在公共电路基底上方和凸起的特征和沟槽上形成电介质膜的第一层，然后对新形成的层进行图案化以去除在凸起特征上形成的层的部分，并暴露凸起特征。在层被图案化之后，通过在图案化的第一层上形成电介质膜的第二层来完成电介质膜的形成。执行附加的膜沉积和膜图案化步骤以在所述公共电路基底上完成薄膜互连结构的布局，并且集成电路管芯附接到公共电路基座并电连接到薄膜互连结构。在优选实施例中，电介质膜的第一和第二层都由光可定义材料形成，并且图案化步骤包括通过对应于凸起特征的图案化掩模将第一层暴露于光，并将曝光层用显影溶液以蚀刻形成在凸起特征上的第一层的部分。

39. 发明授权

US5098527A Method of making electrically conductive patterns 失效
标题翻译：制作电导图案的方法
公开(公告)号：US5098527A
公开(公告)日：1992-03-24
申请号：US408860
申请日：1989-09-18
申请人： Christopher P. Banks , Edward Irving
发明人： Christopher P. Banks , Edward Irving
IPC分类号： C23F1/00 , B23K35/22 , G03F7/00 , G03F7/027 , G03F7/40 , H05K3/00 , H05K3/06 , H05K3/28
CPC分类号： H05K3/061 , B23K35/224 , G03F7/00 , G03F7/40 , H05K3/28 , H05K2203/0571 , H05K2203/0582 , H05K2203/0585 , H05K2203/1105 , H05K2203/135 , H05K3/0076
摘要： A method of making a pattern on an electrically conductive material such as a printed circuit comprises(i) electrodepositing on an electrically conductive surface a film of an organic polymer having, per average molecule, more than one reactive functional group,(ii) forming on the electrodeposited film a predetermined pattern of a heat-curable resist having, per average molecule, more than one group reactive with the reactive groups in the electrodeposited film on heating, thereby leaving predetermined areas of the electrodeposited film uncovered,(iii) removing the uncovered areas of the electrodeposited film by treatment with a solvent therefor, thereby forming a surface comprising bare conductive material in predetermined areas and, in other predetermined areas, conductive material coated by areas of the electrodeposited film covered by the resist, and(iv) heating to complete adhesion of the resist to the electrically conductive surface through the areas of the electrodeposited film covered by the resist,steps (iii) and (iv) being carried out in either order.
摘要翻译：在诸如印刷电路的导电材料上制作图案的方法包括（i）在导电表面上电沉积具有每平均分子多于一个反应性官能团的有机聚合物膜，（ii）在电沉积膜具有每平均分子多于一组的加热可固化抗蚀剂的预定图案，其中加热时与电沉积膜中的反应性基团反应，从而使电沉积膜的预定区域未被覆盖，（iii）除去未覆盖的通过用其溶剂处理电沉积膜的区域，从而在预定区域形成包含裸导电材料的表面，并且在其它预定区域中，由被抗蚀剂覆盖的电沉积膜的区域涂覆的导电材料，和（iv）加热至抗蚀剂通过电沉积f的区域完全粘附在导电表面上由抗蚀剂覆盖的层，步骤（iii）和（iv）以任一顺序进行。

40. 发明授权

US4812388A Process to obtain thin film lines 失效
标题翻译：获得薄膜线的工艺
公开(公告)号：US4812388A
公开(公告)日：1989-03-14
申请号：US102302
申请日：1987-09-25
申请人： Giampiero Ferraris , Antonio Tersalvi
发明人： Giampiero Ferraris , Antonio Tersalvi
IPC分类号： H01L21/30 , G03F7/023 , H01L21/027 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/3205 , H01L21/48 , H05K1/03 , H05K3/00 , H05K3/10 , H05K3/24 , H05K3/38 , G03C5/16
CPC分类号： G03F7/0233 , H01L21/4846 , H05K3/108 , H05K1/0306 , H05K2203/0554 , H05K2203/0577 , H05K2203/0585 , H05K2203/095 , H05K2203/1476 , H05K3/0041 , H05K3/388
摘要： It is described a process to obtain thin film lines by photolithography of thick resist and subsequent selective galvanic growth of gold which enables to obtain very thin lines (2-10 micron) with high definition, that is with nearly vertical walls and with a tolerance in the width of about 1 micron. Such results have been achieved by using polyimide as thick resist, by particular cure cycles of the same polyimide and by a particular dry etching of the polyimide layer to obtain seats in which afterwards the lines become grown.
摘要翻译：描述了通过厚光刻胶的光刻法和随后的金选择性电镀生长获得薄膜线的工艺，其能够以高清晰度获得非常细的线（2-10微米），即具有几乎垂直的壁并且具有公差宽度约为1微米。通过使用聚酰亚胺作为厚抗蚀剂，通过相同聚酰亚胺的特定固化循环和通过对聚酰亚胺层的特定干法蚀刻获得其后生产线的座位已经实现了这些结果。

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