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31. 发明申请

US20080117963A1 Methods and systems for adaptive receiver equalization 有权
标题翻译：自适应接收机均衡的方法和系统
公开(公告)号：US20080117963A1
公开(公告)日：2008-05-22
申请号：US11976185
申请日：2007-10-22
申请人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.
摘要翻译：用于最小化模拟数据信号中的失真的方法和系统包括在接收端均衡模拟数据信号。在一个实施例中，本发明使均衡参数适应于与模拟数据信号相关联的信号路径。自适应控制逻辑由模拟和/或数字组件实现。在一个实施例中，本发明均衡模拟数据信号的谨慎时间模拟表示。在一个实施例中，本发明数字地控制均衡参数。在一个实施例中，所得到的均衡的模拟数据信号被数字化。在示例实现中，对模拟数据信号进行采样，测量样本的质量，并且根据需要使用数字控制来调整一个或多个均衡参数以最小化样本的失真。然后将均衡的样品数字化。本发明适用于低速模拟数据信号和多吉比特数据速率模拟信号。

32. 发明申请

US20060227917A1 High-speed serial data transceiver and related methods 有权
公开(公告)号：US20060227917A1
公开(公告)日：2006-10-12
申请号：US11446144
申请日：2006-06-05
申请人： Aaron Buchwald , Michael Le , Josephus Van Engelen , Xicheng Jiang , Hui Wang , Howard Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Michael Le , Josephus Van Engelen , Xicheng Jiang , Hui Wang , Howard Baumer , Avanindra Madisetti
IPC分类号： H04L7/00
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

33. 发明授权

US06995594B2 Phase interpolator device and method 失效
公开(公告)号：US06995594B2
公开(公告)日：2006-02-07
申请号：US10855392
申请日：2004-05-28
申请人： Aaron W. Buchwald , Myles Wakayama , Michael Le , Jurgen Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron W. Buchwald , Myles Wakayama , Michael Le , Jurgen Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H11/16
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

34. 发明申请

US20040212416A1 Phase interpolator device and method 失效
标题翻译：相位插值器装置及方法
公开(公告)号：US20040212416A1
公开(公告)日：2004-10-28
申请号：US10855392
申请日：2004-05-28
申请人： Broadcom Corporation
发明人： Aaron W. Buchwald , Myles Wakayama , Michael Le , Josephus Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03K003/00
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.
摘要翻译：高速串行数据收发器包括多个接收器和发送器，用于以千兆比特每秒的数据速率接收和发送多个模拟串行数据信号。每个接收机包括用于跟踪与接收机相关联的串行数据信号的相位和频率的定时恢复系统。定时恢复系统包括响应于相位控制信号的相位内插器和具有不同预定相位的一组参考信号。相位内插器导出具有内插相位的采样信号以采样串行数据信号。每个接收机中的定时恢复系统独立地对采样信号和与接收机相关联的串行数据信号进行频率同步。接收机可以包括多个路径，用于根据多个具有内插相位的多个时间交错采样信号对接收的串行数据信号进行采样。

35. 发明授权

US06693860B1 Timing signal recovery by superheterodyne phase locked loop 有权
标题翻译：超外差锁相环定时信号恢复
公开(公告)号：US06693860B1
公开(公告)日：2004-02-17
申请号：US09692309
申请日：2000-10-20
申请人： Michael C. Fischer
发明人： Michael C. Fischer
IPC分类号： G11B700
CPC分类号： H03J7/04 , G11B20/14 , G11B20/1403 , H04L7/0274 , H04L2007/047
摘要： A circuit for recovering the timing reference signal includes a superheterodyne phase locked loop. The recovery circuit avoids the need for a phase linear filter with a large percentage bandwidth and allows placement of the filter at a point in the recovery circuit where the center frequency to be passed is substantially fixed. The recovery circuit thus constructed further allows the bandwidth of the filter to be narrower and tailored to match the modulation characteristics of the timing recovery signal. This further results in a better signal-to-noise ratio into a limiter and phase detector, improving the performance of the phase locked loop.
摘要翻译：用于恢复定时参考信号的电路包括超外差锁相环。恢复电路避免了对具有大百分比带宽的相位线性滤波器的需要，并且允许滤波器放置在恢复电路中要通过的中心频率基本上固定的点处。如此构造的恢复电路进一步允许滤波器的带宽更窄并且被调整以匹配定时恢复信号的调制特性。这进一步导致了更好的信噪比成为限幅器和相位检测器，从而提高了锁相环的性能。

36. 发明申请

US20030141914A1 Phase interpolator device and method 失效
公开(公告)号：US20030141914A1
公开(公告)日：2003-07-31
申请号：US10346210
申请日：2003-01-17
发明人： Aaron W. Buchwald , Myles Wakayama , Michael Le , Josephus Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03K003/00
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

37. 发明申请

US20020039394A1 Phase interpolator device and method 有权
标题翻译：相位插值器装置及方法
公开(公告)号：US20020039394A1
公开(公告)日：2002-04-04
申请号：US09844266
申请日：2001-04-30
发明人： Aaron W. Buchwald , Myles Wakayama , Michael Le , Josephus Van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H04L007/00
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.
摘要翻译：高速串行数据收发器包括多个接收器和发送器，用于以千兆比特每秒的数据速率接收和发送多个模拟串行数据信号。每个接收机包括用于跟踪与接收机相关联的串行数据信号的相位和频率的定时恢复系统。定时恢复系统包括响应于相位控制信号的相位内插器和具有不同预定相位的一组参考信号。相位内插器导出具有内插相位的采样信号以采样串行数据信号。每个接收机中的定时恢复系统独立地对采样信号和与接收机相关联的串行数据信号进行频率同步。接收机可以包括多个路径，用于根据多个具有内插相位的多个时间交错采样信号对接收的串行数据信号进行采样。

38. 发明授权

US5812608A Method and circuit arrangement for processing received signal 失效
标题翻译：用于处理接收信号的方法和电路装置
公开(公告)号：US5812608A
公开(公告)日：1998-09-22
申请号：US642339
申请日：1996-05-03
申请人： Vesa Valimaki , Jukka Henriksson , Timo Laakso
发明人： Vesa Valimaki , Jukka Henriksson , Timo Laakso
IPC分类号： H03H17/06 , H04L7/00 , H04L7/02 , H04L7/027 , H04L27/00 , H04L27/227 , H04N7/24 , G06F17/17
CPC分类号： H04N21/4382 , H03H17/028 , H04L27/2273 , H04L7/0029 , H04N21/2383 , H04L2027/0028 , H04L2027/0057 , H04L7/0062 , H04L7/0274
摘要： The invention is related to a method and circuit arrangement for processing a received signal in a variable symbol rate system, such as a digital television system. In the method and arrangement according to the system, a received signal is sampled at a fixed sampling frequency (f.sub.f) that is higher than the symbol frequency of any one of the received signals. The resulting sample sequence is converted to another sample sequence the sampling frequency of which equals the symbol frequency (f.sub.i) of the received signal or its integer multiple. Then the samples are filtered (8) and signal value decisions are made (9) for the filtered samples. Conversion of the sampling frequency is advantageously performed using a so-called modified Farrow-type fractional delay filter (6) which is controlled using a control signal proportional to the delay of each sample. Using the method and arrangement according to the invention it is possible to process received signals the symbol frequencies of which are arbitrary within set limits.
摘要翻译：本发明涉及用于处理诸如数字电视系统的可变符号率系统中的接收信号的方法和电路装置。在根据系统的方法和装置中，以比接收信号中的任一个的符号频率高的固定采样频率（ff）对接收信号进行采样。所得到的采样序列被转换为其采样频率等于接收信号的符号频率（fi）或其整数倍的另一采样序列。然后对样本进行滤波（8），并对滤波后的样本做出信号值决定（9）。使用所谓的修改的Farrow型小数分数延迟滤波器（6）有利地进行采样频率的转换，其使用与每个样本的延迟成比例的控制信号来控制。使用根据本发明的方法和装置，可以处理其设定限制内的符号频率是任意的接收信号。

39. 发明授权

US5757857A High speed self-adjusting clock recovery circuit with frequency detection 失效
标题翻译：高速自调时钟恢复电路，频率检测
公开(公告)号：US5757857A
公开(公告)日：1998-05-26
申请号：US392958
申请日：1996-03-13
申请人： Aaron W. Buchwald
发明人： Aaron W. Buchwald
IPC分类号： H04L7/027 , H03K7/06 , H03K9/06
CPC分类号： H04L7/0274
摘要： A clock recovery circuit based upon an early-late gate approach is applied to high speed serial communication links using NRZ data. The circuit has no systematic phase offset and therefore requires no external phase adjustment circuits or mechanisms. The circuit is used in high speed integrated receivers for applications including fiber optics, disk-drive read/write electronics, mobile communications and high rate- twisted pair data transmission in multimedia systems. Quadrature samples are obtained and held which follow the shape of the NRZ data transition as a function of phase offset. The data signal is passed through the limiter giving rise to a sawtooth shaped phase error signal. A derivative of the error function is taken to provide a frequency error signal to provide for frequency detection and assistance in frequency acquisition of the phase lock loop circuit generating the recovered clock signal from a variably controlled oscillator.
摘要翻译： PCT No.PCT / US94 / 08223 Sec。 371日期：1996年3月13日 102（e）1996年3月13日PCT 1994年7月21日PCT公布。出版物WO96 / 03800 日期1996年2月8日基于早期门法的时钟恢复电路应用于使用NRZ数据的高速串行通信链路。该电路没有系统的相位偏移，因此不需要外部相位调整电路或机构。该电路用于高速集成接收机，用于多媒体系统中的光纤，磁盘驱动器读/写电子，移动通信和高速双绞线数据传输。获得并保持跟随NRZ数据转换的形状作为相位偏移的函数的正交采样。数据信号通过限幅器，产生锯齿形相位误差信号。采用误差函数的导数来提供频率误差信号，以提供对来自可变控制的振荡器产生恢复的时钟信号的锁相环电路的频率采集的频率检测和辅助。

40. 发明授权

US4977580A Timing and carrier recovery in TDMA without preamble sequence 失效
标题翻译： TDMA无时序和载波恢复
公开(公告)号：US4977580A
公开(公告)日：1990-12-11
申请号：US256958
申请日：1988-10-13
申请人： John D. McNicol
发明人： John D. McNicol
IPC分类号： H04L27/22 , H04J3/00 , H04L7/00 , H04L7/02 , H04L7/027 , H04L7/10 , H04L27/00 , H04L27/227 , H04L27/233
CPC分类号： H04L7/0029 , H04L27/2273 , H04L27/2276 , H04L27/2332 , H04L2027/003 , H04L2027/0048 , H04L2027/0095 , H04L7/0274
摘要： The present invention provides a method of detecting the clock rate and recovering the carrier in a TDMA (time division multiple access) signal. The quadrature baseband components are stored for a predetermined amount of time as sampled data and the clock phase error of the baseband samples are estimated. The clock phase of the baseband samples are corrected from the estimated clock phase error by using interpolation over the sampled quadrature components. The carrier phase error of the stored baseband time corrected quadrature samples are then estimated and the carrier phase is corrected according to the estimated phase error. The corrected clock and carrier signals are then forwarded to decision circuit means for providing demodulated data.
摘要翻译：本发明提供了一种在TDMA（时分多址）信号中检测时钟速率和恢复载波的方法。将正交基带分量作为采样数据存储预定量的时间，并估计基带采样的时钟相位误差。通过对采样的正交分量进行插值，从估计的时钟相位误差校正基带采样的时钟相位。然后估计存储的基带时间校正正交采样的载波相位误差，并根据估计的相位误差校正载波相位。校正的时钟和载波信号然后被转发到用于提供解调数据的判定电路装置。

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