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31. 发明申请

US20170222657A1 HYBRID DIGITAL/ANALOG NOISE SHAPING IN THE SIGMA-DELTA CONVERSION 有权
公开(公告)号：US20170222657A1
公开(公告)日：2017-08-03
申请号：US15421989
申请日：2017-02-01
申请人： Infineon Technologies AG
发明人： Igor Ullmann
IPC分类号： H03M3/00
CPC分类号： H03M3/352 , H03M3/358 , H03M3/414 , H03M3/454 , H03M3/458 , H03M7/3004
摘要： An analog/digital converter (ADC) includes an analog stage with at least one first sigma-delta modulator and includes a digital stage with at least one second sigma-delta modulator. The analog stage is configured for outputting a digital signal to the digital stage that is indicative of a noise contribution of the at least one first sigma-delta modulator. The analog stage and the digital stage may be arranged in a multi-stage noise shaping architecture (MASH) architecture.

32. 发明授权

US09660665B2 Delta sigma modulator with dynamic error cancellation 有权
公开(公告)号：US09660665B2
公开(公告)日：2017-05-23
申请号：US15226436
申请日：2016-08-02
申请人： Texas Instruments Incorporated
发明人： Eeshan Miglani , Karthikeyan Gunasekaran , Santhosh Kumar Gowdhaman , Shagun Dusad
IPC分类号： H03M3/00 , H03M1/74 , H03M1/12 , H03M1/00
CPC分类号： H03M3/50 , H03M1/00 , H03M1/001 , H03M1/0626 , H03M1/0665 , H03M1/12 , H03M1/747 , H03M3/30 , H03M3/34 , H03M3/422 , H03M3/458 , H03M7/3004
摘要： The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

33. 发明授权

US09571107B2 High-order sigma delta for a divider-less digital phase-locked loop 有权
标题翻译：用于无分频数字锁相环的高阶西格玛delta
公开(公告)号：US09571107B2
公开(公告)日：2017-02-14
申请号：US14317435
申请日：2014-06-27
申请人： Intel IP Corporation
发明人： Rotem Banin , Elan Banin , Ofir Degani
IPC分类号： H03L7/08 , H03L7/085 , H04B1/40 , H03L7/16 , H03M7/30
CPC分类号： H03L7/085 , H03L7/16 , H03L2207/50 , H03M7/3004 , H04B1/40
摘要： Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.
摘要翻译：这里描述的是与无分频数字锁相环（DPLL）的实现相关的技术，其包括与较高阶Σ-Δ匹配的环路响应。

34. 发明授权

US09461653B2 Fractional-N phase-locked loop 有权
标题翻译：小数N锁相环
公开(公告)号：US09461653B2
公开(公告)日：2016-10-04
申请号：US14985985
申请日：2015-12-31
申请人： Silicon Laboratories Inc.
发明人： Michael H. Perrott
IPC分类号： H03L7/06 , H03L7/08 , H03L7/093 , H03M1/08 , H03M1/66 , G04F10/00 , H03L7/099 , H03M3/00 , H03L7/085 , H02M3/07 , H03M7/30
CPC分类号： H03L7/0802 , G04F10/005 , H02M3/07 , H03L7/085 , H03L7/093 , H03L7/0995 , H03M1/0836 , H03M1/0854 , H03M1/66 , H03M3/358 , H03M3/368 , H03M7/3004
摘要： A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators.
摘要翻译：锁相环（PLL）包括时间到电压转换器，以将参考信号和PLL的反馈信号之间的相位误差转换成一个或多个电压信号。基于振荡器的模数转换器（ADC）接收一个或多个电压信号，并根据电压控制一个或多个振荡器。基于振荡器的ADC基于一个或多个振荡器的频率来确定对应于相位误差的数字值。

35. 发明授权

US09246500B2 Time-to-voltage converter using a capacitor based digital to analog converter for quantization noise cancellation 有权
标题翻译：使用基于电容器的数模转换器进行量化噪声消除的时间到电压转换器
公开(公告)号：US09246500B2
公开(公告)日：2016-01-26
申请号：US14448466
申请日：2014-07-31
申请人： Silicon Laboratories Inc.
发明人： Michael H. Perrott
IPC分类号： H03L7/06 , H03L7/093 , H03L7/08 , H03M1/08 , H03M1/66 , G04F10/00 , H03L7/099 , H03M3/00 , H03L7/085 , H02M3/07
CPC分类号： H03L7/0802 , G04F10/005 , H02M3/07 , H03L7/085 , H03L7/093 , H03L7/0995 , H03M1/0836 , H03M1/0854 , H03M1/66 , H03M3/358 , H03M3/368 , H03M7/3004
摘要： Quantization noise in a fractional-N phase-locked loop (PLL) is canceled using a capacitor-based digital to analog converter (DAC). A phase error is detected between a reference signal and a feedback signal in the PLL. A charge pump circuit charges a first capacitor circuit based on the phase error to generate a phase error voltage corresponding to the phase error. The capacitor based DAC generates a quantization error correction voltage based on a digital value corresponding to the quantization error, which is then combined with the phase error voltage to cancel the quantization error.
摘要翻译：使用基于电容的数/模转换器（DAC）来消除分数N锁相环（PLL）中的量化噪声。在PLL中的参考信号和反馈信号之间检测到相位误差。电荷泵电路基于相位误差对第一电容器电路充电，以产生与相位误差相对应的相位误差电压。基于电容器的DAC基于与量化误差对应的数字值产生量化误差校正电压，然后将其与相位误差电压组合以消除量化误差。

36. 发明申请

US20150145571A1 CANCELLATION OF DELTA-SIGMA QUANTIZATION NOISE WITHIN A FRACTIONAL-N PLL WITH A NONLINEAR TIME-TO-DIGITAL CONVERTER 有权
标题翻译：在具有非线性时间到数字转换器的分数N PLL中消除DELTA-SIGMA量化噪声
公开(公告)号：US20150145571A1
公开(公告)日：2015-05-28
申请号：US14448447
申请日：2014-07-31
申请人： Silicon Laboratories Inc.
发明人： Michael H. Perrott
IPC分类号： H03L7/093 , H03L7/085
CPC分类号： H03L7/0802 , G04F10/005 , H02M3/07 , H03L7/085 , H03L7/093 , H03L7/0995 , H03M1/0836 , H03M1/0854 , H03M1/66 , H03M3/358 , H03M3/368 , H03M7/3004
摘要： A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.
摘要翻译：分数N锁相环（PLL）包括非线性时间到数字转换器，其产生对应于分数N PLL的反馈信号与参考信号之间的时间差的相位误差的数字表示。非线性量化噪声消除电路提供校正信号以确保生成的数字表示具有降低的量化噪声。校正信号可以应用于模拟或数字域。

37. 发明授权

US08847803B2 Parallel multibit digital-to-digital sigma-delta modulation 有权
标题翻译：并行多位数字到数字Σ-Δ调制
公开(公告)号：US08847803B2
公开(公告)日：2014-09-30
申请号：US13483704
申请日：2012-05-30
申请人： Zhongxuan Zhang , Bernard Ginetti
发明人： Zhongxuan Zhang , Bernard Ginetti
IPC分类号： H03M3/00 , H03M7/30
CPC分类号： H03M7/3002 , H03M7/3004
摘要： Digital input words are received in parallel by a parallel digital-to-digital sigma-delta modulator. Error words corresponding to quantization error are added in parallel to the input words to form encoded data words. The encoded data words are quantized into parallel output words and the error words resulting from such quantization are distributed across parallel modulator stages to effect a predetermined quantization error spectral distribution. The quantized output words are output in parallel.
摘要翻译：数字输入字由并行数字Σ-Δ调制器并行接收。对应于量化误差的错误字与输入字并行地添加以形成编码数据字。编码数据字被量化为并行输出字，并且由这种量化产生的误差字分布在并行调制器级上，以实现预定的量化误差频谱分布。量化输出字并行输出。

38. 发明授权

US08212700B2 Delta-sigma-delta modulator 有权
标题翻译： Delta-Δ-Δ调制器
公开(公告)号：US08212700B2
公开(公告)日：2012-07-03
申请号：US12832703
申请日：2010-07-08
申请人： Luciano Zoso
发明人： Luciano Zoso
IPC分类号： H03M3/00
CPC分类号： H03M3/422 , H03M7/3004
摘要： An Analog-to-Digital Converter (ADC) is provided. An embodiment of the ADC includes a modified Delta modulator including a digital feedback loop, and a digital Sigma-Delta modulator configured within the feedback loop. Embodiments of the invention provide analog functionality with all the benefits of a digital design process as well as various other advantages provided by a Delta-Sigma-Delta modulator configuration.
摘要翻译：提供了一个模数转换器（ADC）。 ADC的实施例包括经修改的Delta调制器，包括数字反馈回路，以及配置在反馈回路内的数字Σ-Δ调制器。本发明的实施例提供具有数字设计过程的所有益处的模拟功能以及由Delta-Sigma-Delta调制器配置提供的各种其它优点。

39. 发明申请

US20110140940A1 COEFFICIENT MULTIPLIER AND DIGITAL DELTA-SIGMA MODULATOR USING THE SAME 有权
标题翻译：使用相同的系数乘法器和数字三角形调制器
公开(公告)号：US20110140940A1
公开(公告)日：2011-06-16
申请号：US12783294
申请日：2010-05-19
申请人： Min Hyung CHO , Yi Gyeong KIM , Jong Kee KWON
发明人： Min Hyung CHO , Yi Gyeong KIM , Jong Kee KWON
IPC分类号： H03M3/00 , G06G7/28
CPC分类号： H03M7/3004 , H03M7/3033 , H03M7/304
摘要： Provided are a coefficient multiplier and digital delta-sigma modulator using the same. The coefficient multiplier has the average of output signals of respective dependent multipliers as an effective coefficient using a coefficient averaging technique without employing an adder that has a complex structure and occupies a large chip area. Accordingly, the coefficient multiplier has a simple hardware constitution and small chip area in comparison with a canonical signed digit (CSD) coefficient multiplier, and the digital delta-sigma modulator employing the coefficient multiplier has a simple structure and small size.
摘要翻译：提供了使用其的系数乘法器和数字Δ-Σ调制器。系数乘法器使用系数平均技术将各自的相关乘法器的输出信号的平均值作为有效系数，而不使用具有复杂结构的加法器并占据较大的码片面积。因此，系数乘法器与典型有符号数（CSD）系数乘法器相比，具有简单的硬件结构和小的芯片面积，并且采用系数乘法器的数字Δ-Σ调制器结构简单，体积小。

40. 发明授权

US07719369B2 Sigma delta digital to analog converter with wide output range and improved linearity 有权
标题翻译： Sigma Delta数模转换器具有宽输出范围和改善的线性度
公开(公告)号：US07719369B2
公开(公告)日：2010-05-18
申请号：US12211834
申请日：2008-09-17
申请人： Anant Shankar Kamath , Biman Chattopadhyay
发明人： Anant Shankar Kamath , Biman Chattopadhyay
IPC分类号： H03L7/099 , H03M1/66 , H03M1/68
CPC分类号： H03L7/093 , H03M1/68 , H03M1/747 , H03M3/502 , H03M7/3004
摘要： A sigma delta DAC using a single DAC to generate a first analog quantity portion and a second analog quantity portion, having a strength respectively proportionate to the most significant bits (MSBs) and least significant bits (LSBs) of a received digital value. The two portions are added to generate an analog output representing the strength of the digital value. In an embodiment, the single DAC contains a set of current sources, with some of the current sources (determined by the value of the MSBs) being connected to provide the corresponding output currents on a first path. Some of the other current sources, determined by a value of the LSBs, are controlled to be connected to provide the corresponding output currents on a second path. The time durations the currents are connected to the second path, are determined by the output of a sigma delta modulator.
摘要翻译：使用单个DAC产生第一模拟量部分和第二模拟量部分的Σ-ΔDAC具有分别与接收数字值的最高有效位（MSB）和最低有效位（LSB）成比例的强度。添加两个部分以产生表示数字值的强度的模拟输出。在一个实施例中，单个DAC包含一组电流源，其中一些电流源（由MSB的值确定）被连接以在第一路径上提供对应的输出电流。由LSB的值确定的一些其他电流源被控制为连接以在第二路径上提供相应的输出电流。电流连接到第二路径的持续时间由Σ-Δ调制器的输出决定。

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