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1. 发明公开

US20240072820A1 Multi-Bit Voltage-to-Delay Conversion in Data Converter Circuitry 审中-公开
公开(公告)号：US20240072820A1
公开(公告)日：2024-02-29
申请号：US17898844
申请日：2022-08-30
申请人： Texas Instruments Incorporated
发明人： Sai Aditya Nurani , Rishi Soundararajan , Nithin Gopinath , Visvesvaraya Pentakota , Shagun Dusad
IPC分类号： H03M1/12 , H03M1/44 , H03M1/50 , H03M1/78
CPC分类号： H03M1/1245 , H03M1/44 , H03M1/50 , H03M1/785
摘要： An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

2. 发明授权

US11489515B2 Clock filter with negative resistor circuit 有权
公开(公告)号：US11489515B2
公开(公告)日：2022-11-01
申请号：US17463588
申请日：2021-09-01
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Eeshan Miglani , Shagun Dusad
IPC分类号： H03H11/12 , G06F1/10 , H03K19/20
摘要： A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter. The filter includes a notch filter and a bandpass filter.

3. 发明申请

US20220173710A1 Balun With Improved Common Mode Rejection Ratio 有权
公开(公告)号：US20220173710A1
公开(公告)日：2022-06-02
申请号：US17411673
申请日：2021-08-25
申请人： Texas Instruments Incorporated
发明人： Shagun Dusad , Vysakh Karthikeyan , Naveen Mahadev , Rafi Mahammad
IPC分类号： H03H7/42 , H01F27/28 , H03H7/00
摘要： A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first parasitic capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second parasitic capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.

4. 发明申请

US20210211102A1 TIME GAIN COMPENSATION CIRCUIT IN AN ULTRASOUND RECEIVER 有权
公开(公告)号：US20210211102A1
公开(公告)日：2021-07-08
申请号：US17210251
申请日：2021-03-23
申请人： Texas Instruments Incorporated
发明人： Vajeed Nimran , Raja Sekhar , Sandeep Oswal , Shagun Dusad
IPC分类号： H03F1/56 , H03F3/45
摘要： The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.

5. 发明授权

US10541700B2 Gain and memory error estimation in a pipeline analog to digital converter 有权
公开(公告)号：US10541700B2
公开(公告)日：2020-01-21
申请号：US16249225
申请日：2019-01-16
申请人： Texas Instruments Incorporated
发明人： Srinivas Kumar Reddy Naru , Narasimhan Rajagopal , Shagun Dusad , Viswanathan Nagarajan , Visvesvaraya Appala Pentakota
IPC分类号： H03M1/06 , H03M1/04 , H03M1/16
摘要： In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

6. 发明申请

US20180262169A1 TIME GAIN COMPENSATION CIRCUIT IN AN ULTRASOUND RECEIVER 审中-公开
公开(公告)号：US20180262169A1
公开(公告)日：2018-09-13
申请号：US15980771
申请日：2018-05-16
申请人： Texas Instruments Incorporated
发明人： Vajeed Nimran , Raja Sekhar , Sandeep Oswal , Shagun Dusad
IPC分类号： H03F1/56 , H03F3/45 , H03G3/30 , H03G1/00
CPC分类号： H03F1/56 , G01S7/52033 , H03F3/45475 , H03F2203/45134 , H03F2203/45151 , H03F2203/45528 , H03F2203/45591 , H03G1/0035 , H03G3/3005 , H03G3/301
摘要： The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.

7. 发明授权

US09660665B2 Delta sigma modulator with dynamic error cancellation 有权
公开(公告)号：US09660665B2
公开(公告)日：2017-05-23
申请号：US15226436
申请日：2016-08-02
申请人： Texas Instruments Incorporated
发明人： Eeshan Miglani , Karthikeyan Gunasekaran , Santhosh Kumar Gowdhaman , Shagun Dusad
IPC分类号： H03M3/00 , H03M1/74 , H03M1/12 , H03M1/00
CPC分类号： H03M3/50 , H03M1/00 , H03M1/001 , H03M1/0626 , H03M1/0665 , H03M1/12 , H03M1/747 , H03M3/30 , H03M3/34 , H03M3/422 , H03M3/458 , H03M7/3004
摘要： The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

8. 发明申请

US20140084982A1 Circuits for Improving Linearity of Metal Oxide Semiconductor (MOS) Transistors 有权
标题翻译：用于改善金属氧化物半导体（MOS）晶体管的线性度的电路
公开(公告)号：US20140084982A1
公开(公告)日：2014-03-27
申请号：US13627396
申请日：2012-09-26
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Shagun Dusad , Visvesvaraya Pentakota
IPC分类号： H03L5/00
CPC分类号： H03K17/16 , H03F1/32 , H03F3/45179 , H03F2203/45394 , H03F2203/45684 , H03F2203/45702 , H03K17/165
摘要： Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region are provided. In one embodiment, a circuit includes an averaging circuit configured to average signals at a drain and a source of a MOS transistor and provide the averaged signal to a gate of the MOS transistor, and one or more current sources coupled with the gate; the circuit is configured to vary voltage at the gate so as to vary a resistance of the MOS transistor. The averaging circuit comprises a first MOS circuit coupled between the drain and the gate, a first capacitor coupled in parallel to the first MOS circuit between the drain and the gate, a second MOS circuit coupled between the source and the gate, and a second capacitor coupled in parallel to the second MOS circuit between the source and the gate.
摘要翻译：提供了构造成改善以线性区域工作的金属氧化物半导体（MOS）晶体管的二阶谐波失真的电路的各种实施例。在一个实施例中，电路包括平均电路，其被配置为平均MOS晶体管的漏极和源极处的信号，并将平均信号提供给MOS晶体管的栅极以及与栅极耦合的一个或多个电流源; 电路被配置为改变栅极处的电压，以便改变MOS晶体管的电阻。平均电路包括耦合在漏极和栅极之间的第一MOS电路，与漏极和栅极之间的第一MOS电路并联耦合的第一电容器，耦合在源极和栅极之间的第二MOS电路和第二电容器在源极和栅极之间并联耦合到第二MOS电路。

9. 发明授权

US11881867B2 Calibration scheme for filling lookup table in an ADC 有权
公开(公告)号：US11881867B2
公开(公告)日：2024-01-23
申请号：US17467561
申请日：2021-09-07
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Narasimhan Rajagopal , Eeshan Miglani , Chirag Chandrahas Shetty , Neeraj Shrivastava , Shagun Dusad , Srinivas Kumar Reddy Naru , Nithin Gopinath , Charls Babu , Shivam Srivastava , Viswanathan Nagarajan , Jagannathan Venkataraman , Harshit Moondra , Prasanth K , Visvesvaraya Appala Pentakota
IPC分类号： H03M1/10
CPC分类号： H03M1/1019
摘要： In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

10. 发明授权

US11831283B2 Time gain compensation circuit in an ultrasound receiver 有权
公开(公告)号：US11831283B2
公开(公告)日：2023-11-28
申请号：US17210251
申请日：2021-03-23
申请人： Texas Instruments Incorporated
发明人： Vajeed Nimran , Raja Sekhar , Sandeep Oswal , Shagun Dusad
IPC分类号： H03F1/56 , H03G1/00 , G01S7/52 , H03F3/45 , H03G3/30
CPC分类号： H03F1/56 , H03F3/45475 , G01S7/52033 , H03F2203/45134 , H03F2203/45151 , H03F2203/45528 , H03F2203/45591 , H03G1/0035 , H03G3/301 , H03G3/3005
摘要： The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.

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