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1. 发明授权

US07403624B2 BTSC encoder and integrated circuit 有权
标题翻译： BTSC编码器和集成电路
公开(公告)号：US07403624B2
公开(公告)日：2008-07-22
申请号：US10744619
申请日：2003-12-23
申请人： Luciano Zoso , Allan P. Chin , David P. Lester
发明人： Luciano Zoso , Allan P. Chin , David P. Lester
IPC分类号： H04R5/00
CPC分类号： H04H20/88
摘要： A BTSC encoder includes dual channel ADC, sync separator, audio processor, filtering device, and a composite audio signal generating device. The filtering device includes a first filter for providing a filtered L+R signal, and a second filter for providing at least one of: i) a filtered and combined pilot and modulated L−R signal and ii) separately filtered pilot and modulated L−R signals. The composite audio signal generating device is responsive to the filtered L+R signal, and at least one of i) the filtered and combined pilot and modulated L−R signal and ii) the separately filtered pilot and modulated L−R signals for generating and outputting a composite analog audio signal. In all embodiments, the modulated L−R signal is filtered via an anti-splatter filter.
摘要翻译： BTSC编码器包括双通道ADC，同步分离器，音频处理器，滤波装置和复合音频信号发生装置。滤波装置包括用于提供经滤波的L + R信号的第一滤波器和用于提供以下各项中的至少一个的第二滤波器：i）经滤波和组合的导频和调制L-R信号，和ii）分别滤波的导频和调制L-R信号。复合音频信号产生装置响应于经滤波的L + R信号，以及i）滤波和组合的导频和调制LR信号中的至少一个，以及ii）分别滤波的导频和调制LR信号，用于产生和输出复合模拟音频信号。在所有实施例中，调制的L-R信号经由防飞溅滤波器被滤波。

2. 发明授权

US07286070B2 RF carrier generator and method thereof 有权
公开(公告)号：US07286070B2
公开(公告)日：2007-10-23
申请号：US11284566
申请日：2005-11-21
申请人： Luciano Zoso , Allan P. Chin , David P. Lester
发明人： Luciano Zoso , Allan P. Chin , David P. Lester
IPC分类号： H03M3/00
CPC分类号： G06F1/025
摘要： An RF carrier generator comprises a circuit for sequentially counting as a function of a randomized offset and time interval, and a memory coupled to the sequential counting circuit. The memory stores samples of a desired Sigma-Delta modulator sequence bit stream. Responsive to an output of the sequential counting circuit, the memory sequentially outputs a single-bit output bit stream of a series of partial sequences of the desired Sigma-Delta modulator sequence bit stream. A method is also disclosed.

3. 发明申请

US20070115158A1 RF carrier generator and method thereof 有权
标题翻译： RF载波发生器及其方法
公开(公告)号：US20070115158A1
公开(公告)日：2007-05-24
申请号：US11284566
申请日：2005-11-21
申请人： Luciano Zoso , Allan Chin , David Lester
发明人： Luciano Zoso , Allan Chin , David Lester
IPC分类号： H03M3/00
CPC分类号： G06F1/025
摘要： An RF carrier generator comprises a circuit for sequentially counting as a function of a randomized offset and time interval, and a memory coupled to the sequential counting circuit. The memory stores samples of a desired Sigma-Delta modulator sequence bit stream. Responsive to an output of the sequential counting circuit, the memory sequentially outputs a single-bit output bit stream of a series of partial sequences of the desired Sigma-Delta modulator sequence bit stream. A method is also disclosed.
摘要翻译： RF载波发生器包括用于根据随机化偏移和时间间隔顺序计数的电路和耦合到顺序计数电路的存储器。存储器存储期望的Σ-Δ调制器序列比特流的样本。响应于顺序计数电路的输出，存储器顺序地输出期望的Σ-Δ调制器序列比特流的一系列部分序列的单比特输出比特流。还公开了一种方法。

4. 发明申请

US20070076121A1 NICAM processor 审中-公开
标题翻译： NICAM处理器
公开(公告)号：US20070076121A1
公开(公告)日：2007-04-05
申请号：US11240315
申请日：2005-09-30
申请人： Luciano Zoso , Allan Chin , David Lester
发明人： Luciano Zoso , Allan Chin , David Lester
IPC分类号： H04N11/00
CPC分类号： H04N5/605
摘要： A NICAM processor comprises a first memory for temporarily storing a current frame of A-channel and B-channel input data, wherein the current frame data is stored into the first memory at a first clock rate. A second memory temporarily stores companded A-channel and B-channel data of a previous frame in a format other than an interleaved format according to NICAM standard requirements. An interleaving circuit reads the previous frame companded data from the second memory at a second clock rate and in a manner for interleaving the previous frame data into the NICAM standard required interleaved format. A bit stream generator generates a first portion of an output bit stream, multiplexes it with a payload portion, and outputs the output bit stream, wherein the first portion comprises a frame alignment word, control information and additional data, and the payload portion comprises the interleaved data of the previous frame. A companding and storing circuit compands the input data of the current frame and stores the companded data into the second memory at a third clock rate and in the format other than the NICAM interleaved format. The companding and storing circuit is operative during an interval within the current frame, subsequent to the storing into the first memory and the reading from the second memory.
摘要翻译： NICAM处理器包括用于临时存储A信道和B信道输入数据的当前帧的第一存储器，其中当前帧数据以第一时钟速率存储到第一存储器中。第二存储器根据NICAM标准要求临时存储除了交织格式之外的格式的前一帧的压缩A信道和B信道数据。交织电路以第二时钟速率从第二存储器读出先前的帧压缩数据，并且以将先前帧数据交织为NICAM标准所需交错格式的方式。比特流生成器生成输出比特流的第一部分，将其与有效载荷部分复用，并输出输出比特流，其中第一部分包括帧对准字，控制信息和附加数据，并且有效载荷部分包括前一帧的交织数据。压缩和存储电路抑制当前帧的输入数据，并以第三时钟速率和除了NICAM交错格式之外的格式将压缩数据存储到第二存储器中。压缩和存储电路在当前帧内的间隔期间，在存储到第一存储器中和从第二存储器读取之后可操作。

5. 发明授权

US08212700B2 Delta-sigma-delta modulator 有权
标题翻译： Delta-Δ-Δ调制器
公开(公告)号：US08212700B2
公开(公告)日：2012-07-03
申请号：US12832703
申请日：2010-07-08
申请人： Luciano Zoso
发明人： Luciano Zoso
IPC分类号： H03M3/00
CPC分类号： H03M3/422 , H03M7/3004
摘要： An Analog-to-Digital Converter (ADC) is provided. An embodiment of the ADC includes a modified Delta modulator including a digital feedback loop, and a digital Sigma-Delta modulator configured within the feedback loop. Embodiments of the invention provide analog functionality with all the benefits of a digital design process as well as various other advantages provided by a Delta-Sigma-Delta modulator configuration.
摘要翻译：提供了一个模数转换器（ADC）。 ADC的实施例包括经修改的Delta调制器，包括数字反馈回路，以及配置在反馈回路内的数字Σ-Δ调制器。本发明的实施例提供具有数字设计过程的所有益处的模拟功能以及由Delta-Sigma-Delta调制器配置提供的各种其它优点。

6. 发明授权

US07653448B2 NICAM processing method 失效
标题翻译： NICAM处理方法
公开(公告)号：US07653448B2
公开(公告)日：2010-01-26
申请号：US11240314
申请日：2005-09-30
申请人： Luciano Zoso , Allan P. Chin , David P. Lester
发明人： Luciano Zoso , Allan P. Chin , David P. Lester
IPC分类号： G06F17/00 , G06F12/06 , H04H20/47 , H04H20/88
CPC分类号： H04N5/605
摘要： A NICAM processing method includes receiving and temporarily storing a current frame of A-channel and B-channel input data into a first memory at a first clock rate. Companded A-channel and B-channel data of a previous frame are read from a second memory at a second clock rate and in a manner for interleaving the previous frame companded A-channel and B-channel data into the NICAM standard required interleaved format, wherein the companded A-channel and B-channel data of the previous frame was temporarily stored during a previous frame into the second memory in a format other than an interleaved format according to NICAM standard requirements. The A-channel and B-channel input data of the current frame is companded and stored into the second memory and in the format other than the interleaved format, wherein the companding and storing are performed at a third clock rate during an interval within the current frame that occurs subsequent to both the storing into the first memory and the reading from the second memory.
摘要翻译： NICAM处理方法包括以第一时钟速率接收和临时存储当前帧的A信道和B信道输入数据到第一存储器中。以第二时钟速率从第二存储器读取先前帧的压缩A信道和B信道数据，并且以将先前帧压缩的A信道和B信道数据交织到NICAM标准所需交织格式的方式，其中根据NICAM标准要求，前一帧的压缩的A信道和B信道数据在前一帧中以不同于交织格式的格式临时存储到第二存储器中。当前帧的A信道和B信道输入数据被压缩并存储到第二存储器中并且以除交织格式之外的格式存储，其中在当前时间间隔内以第三时钟速率执行压扩和存储在存储到第一存储器中以及从第二存储器读取之后发生的帧。

7. 发明申请

US20060244644A1 Variable interpolator for non-uniformly sampled signals and method 失效
标题翻译：用于非均匀采样信号的可变内插器和方法
公开(公告)号：US20060244644A1
公开(公告)日：2006-11-02
申请号：US11394254
申请日：2006-03-30
申请人： Luciano Zoso , Allan Chin , David Lester
发明人： Luciano Zoso , Allan Chin , David Lester
IPC分类号： H03M3/00
CPC分类号： H03H17/0671 , H03H17/0621 , H03H17/0657 , H03H2218/14
摘要： A variable interpolator (110) has an interpolation factor L for performing an interpolation of an input signal (124), where L is variable and includes a minimum value. The variable interpolator includes a differentiator (110-1), a chopper (112), and an integrator (110-2). The differentiator (110-1) is responsive to a signal on the differentiator input for performing a differentiator portion of the interpolation and for providing a differentiator result signal (134). The chopper is coupled with the differentiator for chopping the differentiator result signal as a function of the minimum value of L, wherein for an interpolator input signal that contains non-uniformly sampled signals in which there exists at least one sample of a shortest duration and at least one sample of a duration that extends beyond the shortest duration, the minimum value of L corresponds to the duration of the sample of shortest duration, and wherein for an interpolator input signal that contains uniformly sampled signals in which the samples are of a fixed duration, the minimum value of L corresponds to the fixed duration. The integrator is responsive to the chopped differentiator result signal for performing an integrator portion of the interpolation and for providing an integrator result signal, corresponding to an output (142) of the variable interpolator.
摘要翻译：可变内插器（110）具有用于执行输入信号（124）的内插的内插因子L，其中L是可变的并且包括最小值。可变内插器包括微分器（110-1），斩波器（112）和积分器（110-2）。微分器（110-1）响应微分器输入上的信号，以执行插值的微分器部分并提供微分器结果信号（134）。斩波器与微分器耦合，作为L的最小值的函数斩波微分器结果信号，其中对于包含非均匀采样信号的内插器输入信号，其中存在至少一个具有最短持续时间的样本和持续时间超过最短持续时间的至少一个样本，L的最小值对应于最短持续时间的样本的持续时间，并且其中对于包含均匀采样的信号的内插器输入信号，其中采样具有固定持续时间，L的最小值对应于固定持续时间。积分器响应于斩波微分器结果信号，以执行内插的积分器部分，并提供对应于可变内插器的输出（142）的积分器结果信号。

8. 发明申请

US20050135630A1 BTSC encoder and integrated circuit 有权
标题翻译： BTSC编码器和集成电路
公开(公告)号：US20050135630A1
公开(公告)日：2005-06-23
申请号：US10744619
申请日：2003-12-23
申请人： Luciano Zoso , Allan Chin , David Lester
发明人： Luciano Zoso , Allan Chin , David Lester
IPC分类号： H04H20/88 , H04R5/00
CPC分类号： H04H20/88
摘要： A BTSC encoder includes dual channel ADC, sync separator, audio processor, filtering device, and a composite audio signal generating device. The filtering device includes a first filter for providing a filtered L+R signal, and a second filter for providing at least one of: i) a filtered and combined pilot and modulated L−R signal and ii) separately filtered pilot and modulated L−R signals. The composite audio signal generating device is responsive to the filtered L+R signal, and at least one of i) the filtered and combined pilot and modulated L−R signal and ii) the separately filtered pilot and modulated L−R signals for generating and outputting a composite analog audio signal. In all embodiments, the modulated L−R signal is filtered via an anti-splatter filter.
摘要翻译： BTSC编码器包括双通道ADC，同步分离器，音频处理器，滤波装置和复合音频信号发生装置。滤波装置包括用于提供经滤波的L + R信号的第一滤波器和用于提供以下各项中的至少一个的第二滤波器：i）经滤波和组合的导频和调制L-R信号，和ii）分别滤波的导频和调制L-R信号。复合音频信号产生装置响应于经滤波的L + R信号，以及i）滤波和组合的导频和调制LR信号中的至少一个，以及ii）分别滤波的导频和调制LR信号，用于产生和输出复合模拟音频信号。在所有实施例中，调制的L-R信号经由防飞溅滤波器被滤波。

9. 发明授权

US09281745B2 Digital controller for switch-mode DC-DC converters and method 有权
标题翻译：开关型DC-DC转换器数字控制器及方法
公开(公告)号：US09281745B2
公开(公告)日：2016-03-08
申请号：US14067733
申请日：2013-10-30
申请人： Luciano Zoso , Allan P. Chin
发明人： Luciano Zoso , Allan P. Chin
IPC分类号： H02M3/157 , H02M1/00
CPC分类号： H02M3/157 , H02M2001/0012
摘要： A fully digital synthesizable digital controller (152, 152a) controls a switch-mode DC-DC converter (150, 230, 240, 250, 260) having switching elements (154) and an LC circuit (156, 157) for producing an output voltage (160) that is maintained at a desired level regardless of load changes that can occur on the output. The digital controller (152, 152a) comprises an input stage (164), proportional-integral-derivative (PID) compensator (170), and a digital sigma-delta modulator (172). The input stage (164) produces a difference signal between a reference voltage Vref and a feedback voltage Vfbk, and comprises (i) first and second delta-sigma-delta modulators (178, 180) and a subtractor (182), (ii) a delta-sigma-delta modulator (180) and a subtractor (182); or (iii) a comparator (218). The PID compensator (170) processes the difference signal to compensate for an undesired phase shift and to stabilize the feedback loop. The digital sigma-delta modulator (172) generates a switching element control signal for controlling at least one of the switching elements.
摘要翻译：全数字可合成数字控制器（152,152a）控制具有开关元件（154）和LC电路（156,157）的开关模式DC-DC转换器（150,230,240,250,260），用于产生输出电压（160），其保持在期望的水平，而与输出上可能发生的负载变化无关。数字控制器（152,152a）包括输入级（164），比例积分微分（PID）补偿器（170）和数字Σ-Δ调制器（172）。输入级（164）产生参考电压Vref和反馈电压Vfbk之间的差信号，并且包括（i）第一和第二Δ-Σ-调制器（178,180）和减法器（182），（ii） Δ-Δ-Δ调制器（180）和减法器（182）; 或（iii）比较器（218）。 PID补偿器（170）处理差分信号以补偿不期望的相移并稳定反馈回路。数字Σ-Δ调制器（172）产生用于控制至少一个开关元件的开关元件控制信号。

10. 发明授权

US07512391B2 Self-aligning resonator filter circuit and wideband tuner circuit incorporating same 有权
标题翻译：自调谐谐振滤波电路和并入其的宽带调谐电路
公开(公告)号：US07512391B2
公开(公告)日：2009-03-31
申请号：US11136752
申请日：2005-05-24
申请人： David P. Lester , Allan P. Chin , Luciano Zoso
发明人： David P. Lester , Allan P. Chin , Luciano Zoso
IPC分类号： H04B1/06
CPC分类号： H03J3/185 , H03J3/20 , H03J2200/07 , H03J2200/08 , H03J2200/10 , H03J2200/29
摘要： A self-aligning resonator filter, a self-aligning coupled resonator filter circuit, and a television tuner circuit incorporating the filter and the circuit are disclosed herein. The self-aligning resonator filter leverages the local oscillator of the tuner circuit and can be realized with a significant reduction in the amount of off-chip components. The self-aligning resonator filter is configured to align its tunable resonator to resonate at a desired frequency in response to a phase difference measured across a resistance element during a tuning mode, and the resistance element is switched out of the self-aligning resonator filter during a run mode. The self-aligning coupled resonator filter circuit is configured to isolate its individual resonator stages during tuning such that each resonator stage can be aligned without being influenced by the other resonator stage. The television tuner circuit can be manufactured at relatively low cost while retaining high performance and the ability to be dynamically aligned while in use.
摘要翻译：本文公开了一种自对准谐振器滤波器，自对准耦合谐振器滤波器电路和结合滤波器和电路的电视调谐器电路。自调谐谐振器滤波器利用调谐器电路的本地振荡器，并且可以显着减少芯片外部件的数量。自对准谐振器滤波器被配置为响应于在调谐模式期间跨过电阻元件测量的相位差而使其可调谐谐振器以期望的频率谐振，并且电阻元件在自对准谐振器滤波器期间被切换出自对准谐振器滤波器运行模式。自对准耦合谐振器滤波器电路被配置为在调谐期间隔离其各个谐振器级，使得每个谐振器级可以对准而不受另一个谐振器级的影响。电视调谐器电路可以以相对低的成本制造，同时保持高性能和在使用时动态对准的能力。

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