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    • 37. 发明申请
    • Viterbi decoder
    • 维特比解码器
    • US20060209995A1
    • 2006-09-21
    • US10565377
    • 2004-07-26
    • Nobuhiro Takagi
    • Nobuhiro Takagi
    • H03D1/00H03M13/03
    • H03M13/6337H03M13/23H03M13/41H03M13/4107H03M13/413H03M13/4161H03M13/4169H03M13/4192H03M13/6502H03M13/6516H03M13/6561H04L1/0054
    • A Viterbi decoder capable of supporting a variety of constraint lengths and any arbitrary number of coefficients of a given estimated transmission path and composed of special hardware of small circuit scale. In the Viterbi decoder of the present invention, a branch metric calculation section (101) calculates the branch metrics of all paths from the state of the previous time to the state at the present time, selects the most probable path from the paths arriving at respective states based on the branch metrics (101a) and path metrics (103a) and outputs path select signal (102a) and path metric (102b). Path metric storage section (103) outputs path metric (103a) to be input to ACS calculation section (102) when performing ACS calculating at the next time. Path select signal temporary storage section (104) holds path select signal (102a) of n states, outputs path select signal (104a) of m states (m≦n) and changes a bit input position according to the encoding constraint length or the number of coefficient of deduced estimated transmission path of the system which performs Viterbi decoding.
    • 维特比解码器能够支持各种约束长度和任意数量的给定估计传输路径的系数,并由小电路规模的特殊硬件组成。 在本发明的维特比解码器中,分支度量计算部(101)计算从前一时刻的状态到当前状态的所有路径的分支度量,从到达各自的路径中选择最可能的路径 基于分支度量(101a)和路径度量(103a)的状态,并输出路径选择信号(102a)和路径度量(102b)。 当在下一次执行ACS计算时,路径度量存储部(103)输出要输入到ACS计算部(102)的路径度量(103a)。 路径选择信号临时存储部(104)保持n个状态的路径选择信号(102a),输出m个状态(m <= n)的路径选择信号(104a),并根据编码约束长度改变位输入位置 或执行维特比解码的系统的推定估计传输路径的系数的数量。