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1. 发明申请

US20080005650A1 LDPC (low density parity check) coded modulation hybrid decoding 有权
标题翻译： LDPC（低密度奇偶校验）编码调制混合解码
公开(公告)号：US20080005650A1
公开(公告)日：2008-01-03
申请号：US11701156
申请日：2007-02-01
申请人： Ba-Zhong Shen , Hau Tran , Kelly Cameron
发明人： Ba-Zhong Shen , Hau Tran , Kelly Cameron
IPC分类号： G06F11/00
CPC分类号： H04L1/005 , H03M13/1105 , H03M13/255 , H04L1/0058
摘要： LDPC (Low Density Parity Check) coded modulation hybrid decoding. A novel approach is presented wherein a combination of bit decoding and symbol level decoding (e.g., hybrid decoding) is performed for LDPC coded signals. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until a sufficient degree of precision is achieved. The symbol node updating of the bit edge messages involves using symbol metrics corresponding to the symbol being decoded as well as the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages involves using the bit edge messages most recently updated by symbol node updating. The symbol node updating also involves computing possible soft symbol estimates for the symbol during each decoding iteration.
摘要翻译： LDPC（低密度奇偶校验）编码调制混合解码。提出了一种新颖的方法，其中对LDPC编码信号执行比特解码和符号级解码（例如混合解码）的组合。对于预定数量的解码迭代，或直到达到足够的精确度，连续替代地对位边消息执行检查节点更新和符号节点更新。位边消息的符号节点更新涉及使用与被解码的符号相对应的符号度量以及最近由校验节点更新更新的位边消息。位边消息的校验节点更新涉及使用最近通过符号节点更新更新的位边消息。符号节点更新还涉及在每次解码迭代期间计算符号的可能的软符号估计。

2. 发明授权

US07080310B2 Forward error corrector 失效
公开(公告)号：US07080310B2
公开(公告)日：2006-07-18
申请号：US10733823
申请日：2003-12-11
申请人： Kelly Cameron
发明人： Kelly Cameron
IPC分类号： H03M13/00
CPC分类号： H03M13/153 , H03M13/1525 , H03M13/3746
摘要： A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.

3. 发明申请

US20060045213A1 Decoding error correcting codes transmitted through multiple wire twisted pair cables with uneven noise on the wires 有权
公开(公告)号：US20060045213A1
公开(公告)日：2006-03-02
申请号：US11172551
申请日：2005-06-30
申请人： Ba-Zhong Shen , Scott Powell , Kelly Cameron
发明人： Ba-Zhong Shen , Scott Powell , Kelly Cameron
IPC分类号： H04L27/06
CPC分类号： H04L1/0045 , H03M13/45 , H04L1/02 , H04L25/14 , H04L2001/0096
摘要： Decoding error correcting codes transmitted through multiple wire twisted pair cables with uneven noise on the wires. A novel approach is presented by which the metrics may be calculated for signals received over multi-wire (or alternatively referred to as multi-channel, and/or multi-path) communication channels to exploit an uneven distribution of noise among those wires for improved performance. In addition, this approach may also be performed in combination with employing an amplification factor to modify the metrics employed when performing ECC (Error Correcting Code) decoding. Moreover, when information is known concerning which 1 or more paths (e.g., wires) has an SNR that is different (e.g., lower in some cases) from the others, an even better adapted means of calculating the metrics associated with each of the paths (e.g., wires) may be employed to provide for improved performance with respect to iterative decoding processing of signals encoded using ECCs.

4. 发明申请

US20060041821A1 Short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications 失效
标题翻译：适用于高速以太网应用的短长度LDPC（低密度奇偶校验）码和调制
公开(公告)号：US20060041821A1
公开(公告)日：2006-02-23
申请号：US11190657
申请日：2005-07-27
申请人： Ba-Zhong Shen , Kelly Cameron , Hau Tran , Scott Powell
发明人： Ba-Zhong Shen , Kelly Cameron , Hau Tran , Scott Powell
IPC分类号： H03M13/00
CPC分类号： H04L27/04 , H03M13/118 , H03M13/255 , H04L25/4917 , H04L27/3416
摘要： A short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications. In some instances, the short length-LDPC code and modulation may be employed within the recommended practices currently being developed by the IEEE 802.3an (10GBASE-T) Task Force. The IEEE 802.3an (10GBASE-T) Task Force has been commissioned to develop and standardize communications protocol adapted particularly for Ethernet operation over 4 wire twisted pair cables. A new LDPC code, some possible embodiments of constellations and the corresponding mappings, as well as possible embodiments of various parity check matrices, H, of the LDPC code are presented herein to provide for better overall performance than other proposed LDPC codes existent in the art of high speed Ethernet applications. Moreover, this proposed LDPC code may be decoded using a communication device having much less complexity than required to decode other proposed LDPC codes existent in this technology space.
摘要翻译：适用于高速以太网应用的短长度LDPC（低密度奇偶校验）码和调制。在一些情况下，可以在IEEE 802.3an（10GBASE-T）工作组当前正在开发的推荐做法中采用短长度LDPC码和调制。 IEEE 802.3an（10GBASE-T）工作组已委托开发和标准化通信协议，特别适用于通过4线双绞线电缆进行以太网操作。本文中呈现了新的LDPC码，星座的一些可能的实施例和对应的映射以及LDPC码的各种奇偶校验矩阵H的可能实施例，以提供比本领域中存在的其它提出的LDPC码更好的总体性能的高速以太网应用。此外，该提出的LDPC码可以使用比在该技术空间中存在的其它提出的LDPC码要求更低的复杂度的通信设备进行解码。

5. 发明申请

US20050262421A1 Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders 有权
标题翻译：有效的前端存储器布置支持LDPC（低密度奇偶校验）解码器中的并行比特节点和校验节点处理
公开(公告)号：US20050262421A1
公开(公告)日：2005-11-24
申请号：US11171727
申请日：2005-06-30
申请人： Hau Tran , Kelly Cameron , Ba-Zhong Shen
发明人： Hau Tran , Kelly Cameron , Ba-Zhong Shen
IPC分类号： H03M13/00 , H03M13/11
CPC分类号： H03M13/6563 , H03M13/1137 , H03M13/1165
摘要： Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders. A novel approach is presented by which the front end design of device capable to decode LDPC coded signals facilitates parallel decoding processing of the LDPC coded signal. The implementation of the front end memory management in conjunction with the implementation of a metric generator operate cooperatively lend themselves for very efficient parallel decoding processing of LDPC coded signals. There are several embodiments by which the front end memory management and the metric generator may be implemented to facilitate this parallel decoding processing of LDPC coded signals. This also allows for the decoding of variable code rate and/or variable modulation signals whose code rate and/or modulation varies as frequently as on a block by block basis (e.g., a block may include a group of symbols within a frame).
摘要翻译：有效的前端存储器布置支持LDPC（低密度奇偶校验）解码器中的并行比特节点和校验节点处理。提出了一种能够对LDPC编码信号进行解码的装置的前端设计有助于LDPC编码信号的并行解码处理的新颖方法。结合执行度量发生器的前端存储器管理的实现协同地借助于LDPC编码信号的非常有效的并行解码处理。存在可以实现前端存储器管理和度量生成器以促进LDPC编码信号的这种并行解码处理的几个实施例。这也允许解码可变码率和/或可变调制信号，其码率和/或调制随着逐个块的频率而变化（例如，一个块可以包括帧内的符号组）。

6. 发明申请

US20050186958A1 Multiple input multiple output wireless local area network communications 失效
标题翻译：多输入多输出无线局域网通信
公开(公告)号：US20050186958A1
公开(公告)日：2005-08-25
申请号：US10933586
申请日：2004-09-03
申请人： Christopher Hansen , Jason Trachewsky , Nambirajan Seshadri , Kelly Cameron , Hau Tran , Ba-Zhong Shen
发明人： Christopher Hansen , Jason Trachewsky , Nambirajan Seshadri , Kelly Cameron , Hau Tran , Ba-Zhong Shen
IPC分类号： H04L1/06 , H04Q7/20
CPC分类号： H04L1/0625 , H04L1/0059 , H04L1/0071
摘要： A wireless local area network (WLAN) transmitter includes a MAC module, a PLCP module, and a PMD module. The Medium Access Control (MAC) module is operably coupled to convert a MAC Service Data Unit (MSDU) into a MAC Protocol Data Unit (MPDU) in accordance with a WLAN protocol. The Physical Layer Convergence Procedure (PLCP) Module is operably coupled to convert the MPDU into a PLCP Protocol Data Unit (PPDU) in accordance with the WLAN protocol. The Physical Medium Dependent (PMD) module is operably coupled to convert the PPDU into a plurality of radio frequency (RF) signals in accordance with one of a plurality of operating modes of the WLAN protocol, wherein the plurality of operating modes includes multiple input and multiple output combinations.
摘要翻译：无线局域网（WLAN）发送机包括MAC模块，PLCP模块和PMD模块。媒体访问控制（MAC）模块可操作地耦合以根据WLAN协议将MAC服务数据单元（MSDU）转换成MAC协议数据单元（MPDU）。物理层会聚过程（PLCP）模块可操作地耦合，以根据WLAN协议将MPDU转换成PLCP协议数据单元（PPDU）。物理媒体相关（PMD）模块可操作地耦合以根据WLAN协议的多种操作模式之一将PPDU转换成多个射频（RF）信号，其中多个操作模式包括多个输入和多个输出组合。

7. 发明申请

US20050149844A1 Decoding LDPC (low density parity check) code with new operators based on min* operator 有权
标题翻译：基于min *运算符对新算子解码LDPC（低密度奇偶校验）码
公开(公告)号：US20050149844A1
公开(公告)日：2005-07-07
申请号：US11017403
申请日：2004-12-20
申请人： Hau Tran , Ba-Zhong Shen , Kelly Cameron
发明人： Hau Tran , Ba-Zhong Shen , Kelly Cameron
IPC分类号： H03M13/11 , H03M13/25 , H04L1/00 , H04B1/66 , G06F11/00 , H03M13/00 , H04N7/12 , H04N11/02 , H04N11/04
CPC分类号： H04L1/005 , H03M13/1117 , H03M13/112 , H03M13/1165 , H03M13/251 , H03M13/255 , H03M13/6502 , H03M13/658 , H04L1/0058
摘要： Decoding LDPC (Low Density Parity Check) code with new operators based on min* operator. New approximate operators are provided that may be employed to assist in calculating one or a minimum value (or a maximum value) when decoding various coded signals. In the context of LDPC decoding that involves both bit node processing and check node processing, either of these new operators (i.e., the min† (min-dagger) operator or the min′ (min-prime) operator) may be employed to perform the check node processing that involves updating the edge messages with respect to the check nodes. Either of these new operators, min† operator or min′ operator, is shown herein to be a better approximate operator to the min** operator.
摘要翻译：基于min *运算符对新的运算符解码LDPC（低密度奇偶校验）码。提供了新的近似运算符，其可用于在解码各种编码信号时协助计算一个或最小值（或最大值）。在涉及位节点处理和校验节点处理的LDPC解码的上下文中，可以使用这些新的运算符（即，最小†（最小匕首）运算符或最小'（最小素数）运算符）中的任一个来执行检查节点处理涉及相对于校验节点更新边缘消息。这些新操作符中的任一个，min†操作符或min'操作符在本文中显示为对最小**操作符的更好的近似操作符。

8. 发明申请

US20050149843A1 Bandwidth efficient coded modulation scheme based on MLC (multi-level code) signals having multiple maps 有权
标题翻译：基于具有多个映射的MLC（多级代码）信号的带宽高效编码调制方案
公开(公告)号：US20050149843A1
公开(公告)日：2005-07-07
申请号：US11017087
申请日：2004-12-20
申请人： Ba-Zhong Shen , Hau Tran , Kelly Cameron
发明人： Ba-Zhong Shen , Hau Tran , Kelly Cameron
IPC分类号： H03M13/11 , H03M13/25 , H03M13/29 , H03M13/41 , H03M13/45 , H04L1/00 , H04L27/18 , H03D1/00 , G06F11/00 , H03M13/00 , H04L27/06
CPC分类号： H04L1/005 , H03M5/20 , H03M13/1102 , H03M13/1105 , H03M13/1111 , H03M13/1148 , H03M13/1177 , H03M13/255 , H03M13/256 , H03M13/258 , H03M13/2957 , H03M13/4161 , H03M13/45 , H03M13/6561 , H04L1/0041 , H04L1/0058 , H04L1/006 , H04L1/0071 , H04L27/18 , H04L27/183 , H04L27/186 , H04L27/2053
摘要： Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon's limit. In the instance of LDPC coded signals, various level LDPC codewords are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks. Encoded bits from multiple level LDPC codewords within each of the sub-blocks are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.
摘要翻译：基于具有多个映射的MLC（多级代码）信号的带宽高效编码调制方案。多个地图的使用适用于各种类型的编码信号，包括多级LDPC编码调制信号和其他MLC信号，以便在试图达到香农限制的持续努力中提供显着的性能增益。在LDPC编码信号的情况下，从各自对应的LDPC编码器生成各种级别的LDPC码字。这些各种级别的LDPC码字被排列成多个子块。每个子块内的多级LDPC码字的编码比特被排列成根据至少两个调制映射的符号。每个调制包括星座形状和相应的映射。与仅使用单个映射的编码器相比，使用多个映射提供了改进的性能。

9. 发明授权

US06697975B2 Generalized convolutional interleaver/deinterleaver 有权
公开(公告)号：US06697975B2
公开(公告)日：2004-02-24
申请号：US10325525
申请日：2002-12-19
申请人： Kelly Cameron
发明人： Kelly Cameron
IPC分类号： G11C2900
CPC分类号： H03M13/2782 , H03M13/00 , H03M13/2732 , H03M13/276 , H03M13/2789
摘要： A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

10. 发明授权

US5099482A Apparatus for detecting uncorrectable error patterns when using Euclid's algorithm to decode Reed-Solomon (BCH) codes 失效
标题翻译：当使用欧几里德算法解码里德 - 所罗门（BCH）码时，用于检测不可校正错误模式的装置
公开(公告)号：US5099482A
公开(公告)日：1992-03-24
申请号：US400447
申请日：1989-08-30
申请人： Kelly Cameron
发明人： Kelly Cameron
IPC分类号： H03M13/15
CPC分类号： H03M13/15
摘要： A Reed-Solomon Galois Field Euclid algorithm decoder determines whether an error is uncorrectable by checking for:I. deg [.LAMBDA.(x))].ltoreq.tII. deg [.OMEGA.(x)]
摘要翻译： Reed-Solomon Galois Field Euclid算法解码器通过检查以下方式确定误差是否不可校正：I. deg [LAMBDA（x））]

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