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31. 发明申请

US20160226500A1 PLL AND ADAPTIVE COMPENSATION METHOD IN PLL 有权
标题翻译： PLL中的PLL和自适应补偿方法
公开(公告)号：US20160226500A1
公开(公告)日：2016-08-04
申请号：US15021867
申请日：2013-09-22
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
发明人： Zhongyuan Zhao , Weixu Wang , Luping Pan
IPC分类号： H03L7/093 , G01P15/097 , H03G3/20
CPC分类号： H03L7/093 , G01P15/097 , H03G3/20 , H03L1/00 , H03L7/099
摘要： In a method for mitigating the vibration-induced phase noise of an phase locked loop with an acceleration sensitive voltage controlled oscillator, a correction signal generated by applying a gain and a equalization to an acceleration signal provided by an acceleration sensor sensing the acceleration on the VCO, is added to the oscillator control signal for active compensation, an adaptive compensation unit dynamically adjusts the gain, the frequency response of equalization, and the sensing direction of the acceleration sensor while the phase locked loop is working to make the active compensation automatically adapt to the parameters of the voltage controlled oscillator.
摘要翻译：在利用加速度敏感电压控制振荡器来减轻锁相环振动引起的相位噪声的方法中，通过对感测VCO上的加速度的加速度传感器提供的加速度信号应用增益和均衡产生的校正信号，被添加到用于有源补偿的振荡器控制信号中，自适应补偿单元在锁相环工作时动态地调节增益，均衡的频率响应和加速度传感器的感测方向，使得主动补偿自动适应压控振荡器的参数。

32. 发明申请

US20160226496A1 INTEGRATED CIRCUIT DEVICE HAVING AN INJECTION-LOCKED OSCILLATOR 有权
公开(公告)号：US20160226496A1
公开(公告)日：2016-08-04
申请号：US15009485
申请日：2016-01-28
申请人： Rambus Inc.
发明人： Marko Aleksic , Brian S. Leibowitz
IPC分类号： H03L1/00 , H03L7/24
CPC分类号： H03L1/00 , H03K3/0315 , H03L7/083 , H03L7/24
摘要： A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.

33. 发明授权

US09319031B2 High-speed CMOS ring voltage controlled oscillator with low supply sensitivity 有权
标题翻译：具有低电源灵敏度的高速CMOS环形压控振荡器
公开(公告)号：US09319031B2
公开(公告)日：2016-04-19
申请号：US14225079
申请日：2014-03-25
申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
发明人： Michael M. Green , Xiaoyan Gui
IPC分类号： H03K3/03 , H03K3/011 , H03B5/04 , H03B27/00 , H03L1/00
CPC分类号： H03K3/0322 , H03B5/04 , H03B27/00 , H03B2201/038 , H03B2202/042 , H03K3/011 , H03L1/00
摘要： High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator comprises a CML negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation. An impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.
摘要翻译：已经公开了具有低供应灵敏度的高速CMOS环形电压控制振荡器。根据一个实施例，CML环形振荡器包括CML负阻抗补偿电路，其包括两个交叉耦合晶体管和连接到两个用于电阻偏置的晶体管的电阻器以及与CML负阻抗补偿并联连接的CML内插延迟单元。由于电源变化引起的CML负阻抗补偿的阻抗变化抵消了CML内插延迟单元的阻抗变化。

34. 发明申请

US20160079992A1 SYSTEMS AND METHODS FOR FREQUENCY DOMAIN CALIBRATION AND CHARACTERIZATION 审中-公开
标题翻译：用于频域校准和表征的系统和方法
公开(公告)号：US20160079992A1
公开(公告)日：2016-03-17
申请号：US14857145
申请日：2015-09-17
申请人： Intel Corporation
发明人： Cho-Ying Lu , William Yee Li , Khoa Minh Nguyen , Ashoke Ravi , Maneesha Yellepeddi , Binta M. Patel
IPC分类号： H03L7/099 , H03L7/08 , H03L1/00
CPC分类号： H03L7/085 , H03L1/00 , H03L7/08 , H03L7/091 , H03L7/0991 , H03L7/0992 , H03L2207/50
摘要： A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.
摘要翻译：公开了一种用于分配表征和校准参数的系统。该系统包括频率测量电路和有限状态机。频率测量电路被配置为测量振荡信号的频率并产生包括测量频率的测量信号。有限状态机被配置为通过频率测量电路来控制测量，基于测量信号为参数分配表征，并且基于所表征的参数来产生校准信号。

35. 发明授权

US09281779B2 Structure for an inductor-capacitor voltage-controlled oscillator 有权
标题翻译：电感 - 电容压控振荡器的结构
公开(公告)号：US09281779B2
公开(公告)日：2016-03-08
申请号：US14491037
申请日：2014-09-19
申请人： GLOBALFOUNDRIES INC.
发明人： Herschel A. Ainspan , Ram Kelkar , Anjali R. Malladi , Ramana M. Malladi
IPC分类号： H03L1/00 , H03B5/04 , H03B5/12 , H03B7/02 , G06F17/50 , H03B7/06 , H03L7/04
CPC分类号： H03B5/1265 , G06F17/5045 , H03B5/04 , H03B5/1206 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/1253 , H03B7/02 , H03B7/06 , H03B2200/004 , H03B2200/005 , H03B2201/0208 , H03B2202/042 , H03L1/00 , H03L7/04
摘要： Embodiments of the present invention provide a design structure and method for compensating for a change in frequency of oscillation (FOO) of an LC-tank VCO that includes a first node; second node; inductor; first capacitive network (FCN) that allows the design structure to obtain a target FOO; compensating capacitive (CCN) network that compensates for a change in the design structure's FOO; second capacitive network (SCN) that allows the design structure to obtain a desired FOO; a filter that supplies a voltage to the SCN and is coupled to the SCN; a transconductor that compensates for a change in the design structure's FOO; and a sub-circuit coupled to the SCN that generates and supplies voltage to the CCN sufficient to allow the CCN to compensate for a reduction in the design structure's FOO. The first and second nodes are coupled to the inductor, FCN, CCN, SCN, and sub-circuit.
摘要翻译：本发明的实施例提供了一种用于补偿包括第一节点的LC槽VCO的振荡频率（FOO）变化的设计结构和方法; 第二节点电感; 第一电容网络（FCN），允许设计结构获得目标FOO; 补偿电容（CCN）网络，补偿设计结构的FOO的变化; 第二电容网络（SCN），其允许设计结构获得期望的FOO; 一个向SCN提供电压并耦合到SCN的滤波器; 一种补偿设计结构FOO变化的跨导体; 以及耦合到SCN的子电路，其产生并向CCN提供足够的电压以允许CCN补偿设计结构的FOO的减少。第一和第二节点耦合到电感器，FCN，CCN，SCN和子电路。

36. 发明申请

US20150338456A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20150338456A1
公开(公告)日：2015-11-26
申请号：US14816591
申请日：2015-08-03
申请人： SK hynix Inc.
发明人： Young Suk SEO , Ho Uk SONG , Jun Hyun CHUN , Tae Jin KANG
IPC分类号： G01R31/26 , H03L7/06 , H03L1/00
CPC分类号： G01R31/2644 , G01R31/2607 , G11C7/222 , G11C29/023 , G11C29/028 , G11C29/12015 , G11C29/50012 , H03L1/00 , H03L7/06
摘要： A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.
摘要翻译：一种半导体装置，包括：输出定时控制器，被配置为将施加的外部读取命令延迟预定时间，并且在正常模式期间产生正常输出使能标志信号，所述测试输出定时控制器被配置为从外部产生DLL时钟信号时钟信号，与DLL时钟信号同步地延迟施加的外部读取命令，并且在测试模式期间输出延迟的外部应用外部读取命令作为测试输出使能标志信号，以及多路复用器（MUX），其被配置为输出任何一个正常输出使能标志信号或测试输出使能标志信号作为输出使能标志信号。

37. 发明授权

US09182779B1 Jitter compensated numerically controlled oscillator 有权
标题翻译：抖动补偿数控振荡器
公开(公告)号：US09182779B1
公开(公告)日：2015-11-10
申请号：US14216395
申请日：2014-03-17
申请人： Marvell International Ltd.
发明人： Robert Mack , Timothy Chen
IPC分类号： G06F1/02 , H03B28/00 , H03L1/00 , G06F1/03 , H03L7/099
CPC分类号： G06F1/022 , G06F1/0328 , G06F1/08 , H03B28/00 , H03B2200/0088 , H03L1/00 , H03L7/0994
摘要： A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.
摘要翻译：一种用于通过改变用于增加NCO中的累加器的步长值来补偿NCO抖动以补偿不准确或不稳定的方法。在一种方法中，可以监视累加器中的余数，并且可以产生接近理想时钟的当前边缘的补偿时钟。在另一种方法中，在理想时钟的当前边缘被错过之后，可以产生靠近理想时钟的下一个边缘的补偿时钟。步数值可以存储在可以是寄存器的存储器中。抖动补偿器可以包括用于监视累加器中的余数的比较器或用于检测是否错过理想时钟的检测器。抖动补偿器还可以将步长值改变为更快时钟的步进值以补偿抖动。

38. 发明授权

US09148153B2 Systems and methods for frequency domain calibration and characterization 有权
标题翻译：用于频域校准和表征的系统和方法
公开(公告)号：US09148153B2
公开(公告)日：2015-09-29
申请号：US14143116
申请日：2013-12-30
申请人： Intel Corporation
发明人： Cho-Ying Lu , William Yee Li , Khoa Minh Nguyen , Ashoke Ravi , Maneesha Yellepeddi , Binta M. Patel
IPC分类号： H03L7/06 , H03L1/00 , H03L7/099 , H03L7/08
CPC分类号： H03L7/085 , H03L1/00 , H03L7/08 , H03L7/091 , H03L7/0991 , H03L7/0992 , H03L2207/50
摘要： A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.
摘要翻译：公开了一种用于分配表征和校准参数的系统。该系统包括频率测量电路和有限状态机。频率测量电路被配置为测量振荡信号的频率并产生包括测量频率的测量信号。有限状态机被配置为通过频率测量电路来控制测量，基于测量信号为参数分配表征，并且基于所表征的参数来产生校准信号。

39. 发明申请

US20150256188A1 PHASE-LOCKED LOOP CIRCUIT INCLUDING VOLTAGE DOWN CONVERTER CONSISTING OF PASSIVE ELEMENT 有权
标题翻译：封闭式循环电路包括无源元件的降压转换器
公开(公告)号：US20150256188A1
公开(公告)日：2015-09-10
申请号：US14635252
申请日：2015-03-02
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Heechai KANG
IPC分类号： H03L7/099 , H03L7/08
CPC分类号： H03L7/099 , H03L1/00 , H03L7/0802 , H03L7/093
摘要： A phase-locked loop circuit includes a first circuit, a second circuit, and a voltage down converter. The first circuit generates a first signal based on a reference signal and a feedback signal, and operates based on a first supply voltage. The second circuit generates an oscillation signal based on a second signal, generates the feedback signal by dividing the oscillation signal, and operates based on a second supply voltage lower than the first supply voltage. The voltage down converter generates the second signal by decreasing an activation voltage level of the first signal. The voltage down converter includes at least one passive element electrically connected between the first circuit and the second circuit.
摘要翻译：锁相环电路包括第一电路，第二电路和降压转换器。第一电路基于参考信号和反馈信号产生第一信号，并且基于第一电源电压进行操作。第二电路基于第二信号产生振荡信号，通过分频振荡信号产生反馈信号，并且基于低于第一电源电压的第二电源电压进行操作。降压转换器通过降低第一信号的激活电压电平来产生第二信号。所述降压转换器包括电连接在所述第一电路和所述第二电路之间的至少一个无源元件。

40. 发明申请

US20150244381A9 DELAY-LOCKED LOOP WITH DUAL LOOP FILTERS FOR FAST RESPONSE AND WIDE FREQUENCY AND DELAY RANGE 审中-公开
标题翻译：具有双循环滤波器的延迟环路用于快速响应和宽频率和延迟范围
公开(公告)号：US20150244381A9
公开(公告)日：2015-08-27
申请号：US14231730
申请日：2014-03-31
申请人： MoSys, Inc.
发明人： Prashant Choudhary , Aldo Bottelli , Charles W. Boecker
IPC分类号： H03L7/07
CPC分类号： H03L1/00 , H03L7/07 , H03L7/08 , H03L7/0816 , H04L7/0338
摘要： A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
摘要翻译：延迟锁定环路包括用于控制延迟锁定环路中的延迟元件的两个反馈回路。第一反馈回路包括反馈电路，用于基于延迟锁定环路的输入时钟信号与由延迟锁定环路产生的输出时钟信号之间的相位差产生指示延迟调整的反馈信号。第二反馈回路包括功率调节器，其通过使用反馈信号作为参考来调节电源来产生调节信号。延迟锁定环路还包括包括电阻 - 电容网络的可变延迟电路。可变延迟电路基于反馈信号控制电阻 - 电容网络中的电容，并根据调节信号控制电阻 - 电容网络的电阻。以这种方式，可变延迟电路通过基于反馈信号和调节信号两者延迟输入时钟信号来产生输出时钟信号。

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