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31. 发明申请

US20050047204A1 Ferromagnetic layer compositions and structures for spin polarized memory device 有权
标题翻译：铁磁层组成和自旋极化记忆装置的结构
公开(公告)号：US20050047204A1
公开(公告)日：2005-03-03
申请号：US10962253
申请日：2004-10-08
申请人： Mark Johnson
发明人： Mark Johnson
IPC分类号： G01R33/06 , G11B5/37 , G11C7/00 , G11C11/00 , G11C11/16 , G11C11/18 , G11C11/56 , H01L27/22 , H01L29/66 , H01L43/06 , H03K19/18
CPC分类号： H01L43/06 , G01R33/06 , G01R33/1284 , G11B5/378 , G11C11/16 , G11C11/18 , G11C11/5607 , H01L27/222 , H01L27/224 , H01L27/228 , H01L29/66984 , H03K19/18
摘要： Ferromagnetic materials for use with spin memory and logic devices include a geometry and composition adapted to increase spin injection efficiency and/or reduce fringe fields. The ferromagnetic materials can be oriented to implement a variable spin resistance. The ferromagnetic layers are fabricated to permit the device to have two stable magnetization states, parallel and antiparallel. In the “on” state the device has two settable, stable resistance states determined by the relative orientation of the magnetizations of the ferromagnetic layers. An external magnetic field can change the magnetization state of the device by orienting the magnetization of the ferromagnetic layers to be parallel or antiparallel, thus changing the resistance of the device to a current of spin polarized electrons.
摘要翻译：用于自旋存储器和逻辑器件的铁磁材料包括适于增加自旋注入效率和/或减少边缘场的几何形状和组成。铁磁材料可以被定向以实现可变的耐旋转阻力。制造铁磁层以允许器件具有平行和反平行的两个稳定的磁化状态。在“接通”状态下，器件具有由铁磁层的磁化的相对定向决定的两个可设定的稳定的电阻状态。外部磁场可以通过将铁磁层的磁化取向为平行或反平行来改变器件的磁化状态，从而将器件的电阻改变为自旋极化电子的电流。

32. 发明授权

US5654566A Magnetic spin injected field effect transistor and method of operation 失效
公开(公告)号：US5654566A
公开(公告)日：1997-08-05
申请号：US643804
申请日：1996-05-06
申请人： Mark B. Johnson
发明人： Mark B. Johnson
IPC分类号： G11B5/37 , G11C11/16 , G11C11/18 , G11C11/56 , H01L29/66 , H01L43/06 , H03K19/18 , H01L29/82 , H01L43/00
CPC分类号： G11C11/16 , G11C11/18 , G11C11/5607 , H01L29/66984 , H03K19/168 , H03K19/18 , G11B5/378
摘要： A new hybrid magnetic spin injected-FET structure can be used as a memory element for the nonvolatile storage of digital information, as well as in other environments, including for example logic applications for performing digital combinational tasks, or a magnetic field sensor. The hybrid FET uses ferromagnetic materials for the source and drain, and like a conventional FET, has two operating states determined by a gate voltage, "off" and "on". The ferromagnetic layers of the hybrid FET are fabricated to permit the device to have two stable magnetization states, parallel and antiparallel. In the "on" state the spin injected FET has two settable, stable resistance states determined by the relative orientation of the magnetizations of the ferromagnetic source and drain. An external magnetic field can change the magnetization state of the device by orienting the magnetization of the drain to be parallel or antiparallel with that of the source, thus changing the resistance of the device to a current of spin polarized electrons injected into the source and flowing to the drain through the channel under the gate. The new FET can be used as a memory cell because the drain magnetization is non-volatile, and can represent a binary data value to be stored in the cell. A conductive write line can be used for inductively coupling an input magnetic field (representing a data value to be stored in the device) with the drain magnetization to alter the orientation state of the latter. An array of spin injected FETs can be coupled together in an array to form a new hybrid FET memory array. The new FET can also be used as a logic gate that stores the result of a boolean function. A magnetic field generated by the combined current of one or more input data signals is coupled to the spin injected FET. Depending on the particular function to be implemented, the ferromagnetic drain magnetization can be configured to change or retain its orientation based on particular predefined combinations of input data signals.

33. 发明公开

US20240313782A1 CHAOTIC COMPUTER INCLUDING SPIN SOLITON, OPERATION METHOD OF CHAOTIC COMPUTER, AND CHAOTIC COMPUTING METHOD USING SPIN SOLITON 审中-公开
公开(公告)号：US20240313782A1
公开(公告)日：2024-09-19
申请号：US18410351
申请日：2024-01-11
申请人： Samsung Electronics Co., Ltd.
发明人： Sang-Koog KIM , Junhoe KIM , Gyuyoung PARK , Gwanhyeob KOH , Kilho LEE
IPC分类号： H03K19/23 , H03K19/18
CPC分类号： H03K19/23 , H03K19/18
摘要： An operating method of a chaotic computer including a chaotic logic device includes setting a first initial value based on a first initial state corresponding to a first logical operation, applying the set first initial value to the chaotic logic device, setting a first input value to be applied to the chaotic logic device based on first input data, applying the first input value to the chaotic logic device, generating a chaos signal to have the chaotic logic device operate in a chaotic mode, applying the chaos signal to the chaotic logic device, and measuring a first output value from the chaotic logic device operating based on the first input value and the chaos signal, and generating first output data based on the first output value. The chaotic logic device includes a magnetic thin film configured to have spin soliton formed therein.

34. 发明授权

US12068746B2 Magnetic logic device, circuit having magnetic logic devices, and methods for controlling the magnetic logic device and the circuit 有权
公开(公告)号：US12068746B2
公开(公告)日：2024-08-20
申请号：US17773945
申请日：2020-11-02
申请人： Nanyang Technological University
发明人： Chu Keong Gerard Joseph Lim , Chandrasekhar Murapaka , Wen Siang Lew
IPC分类号： G11C11/16 , G11C11/18 , H03K19/18 , H03K19/21 , H10N52/00
CPC分类号： H03K19/18 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/18 , H03K19/21 , H10N52/00
摘要： A magnetic logic device having two magnetic elements and a conductive element coupled to the two magnetic elements and arranged at least substantially perpendicular to the magnetic elements, wherein the device is configured, for each magnetic element, to have a magnetisation state with a perpendicular easy axis, and to switch the magnetisation state in response to a spin current generated in the magnetic element in response to a write current applied to the magnetic element, and configured to generate, as an output, a Hall voltage across the conductive element in response to a respective read current applied to each magnetic element, wherein a magnitude of the Hall voltage is variable, depending on a direction of the magnetisation state of each magnetic element and a direction of the respective read current applied to each magnetic element, for the device to provide outputs corresponding to one of a plurality of logical operations.

35. 发明授权

US11990899B2 Multi-level spin logic 有权
公开(公告)号：US11990899B2
公开(公告)日：2024-05-21
申请号：US17152552
申请日：2021-01-19
申请人： Intel Corporation
发明人： Sasikanth Manipatruni , Ian A. Young , Dmitri E. Nikonov , Uygar E. Avci , Patrick Morrow , Anurag Chaudhry
IPC分类号： H03K19/173 , H03K19/00 , H03K19/18 , H10N50/85 , H10N52/00 , H10N52/80
CPC分类号： H03K19/0002 , H03K19/18 , H10N50/85 , H10N52/00 , H10N52/80
摘要： Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

36. 发明公开

US20240047115A1 SWITCHING OF PERPENDICULARLY MAGNETIZED NANOMAGNETS WITH SPIN-ORBIT TORQUES IN THE ABSENCE OF EXTERNAL MAGNETIC FIELDS 审中-公开
公开(公告)号：US20240047115A1
公开(公告)日：2024-02-08
申请号：US18123418
申请日：2023-03-20
申请人： University of Rochester
发明人： Mohammad Kazemi , Eby G. Friedman , Engin Ipek
IPC分类号： H01F10/32 , G11C11/16 , H03K19/18 , H10N50/00 , H10N50/85 , H10N52/00 , H10N52/80 , G11C11/18
CPC分类号： H01F10/3286 , G11C11/161 , H03K19/18 , G11C11/1675 , H01F10/329 , H10N50/00 , H10N50/85 , H10N52/00 , H10N52/80 , H10N52/101 , G11C11/18 , Y10S148/109
摘要： A method of controlling a trajectory of a perpendicular magnetization switching of a ferromagnetic layer using spin-orbit torques in the absence of any external magnetic field includes: injecting a charge current Je through a heavy-metal thin film disposed adjacent to a ferromagnetic layer to produce spin torques which drive a magnetization M out of an equilibrium state towards an in-plane of a nanomagnet; turning the charge current Je off after te seconds, where an effective field experienced by the magnetization of the ferromagnetic layer Heff is significantly dominated by and in-plane anisotropy Hkx, and where M passes a hard axis by precessing around the Heff; and passing the hard axis, where Heff is dominated by a perpendicular-to-the-plane anisotropy Hkz, and where M is pulled towards the new equilibrium state by precessing and damping around Heff, completing a magnetization switching.

37. 发明授权

US11875272B2 Probabilistic compute engine using coupled ring oscillators 有权
公开(公告)号：US11875272B2
公开(公告)日：2024-01-16
申请号：US17213396
申请日：2021-03-26
申请人： Regents of the University of Minnesota
发明人： Hyung-il Kim , Ibrahim Ahmed , Po-wei Chiu
IPC分类号： G06N5/01 , G06N5/04 , H03K3/03 , G06N10/00 , G06F17/11 , G06N7/01 , H03K5/19 , B82Y10/00 , H03K19/18 , G06N7/08 , G06F17/10
CPC分类号： G06N5/01 , B82Y10/00 , G06F17/10 , G06F17/11 , G06N5/04 , G06N7/01 , G06N7/08 , G06N10/00 , H03K3/0315 , H03K5/19 , H03K19/18
摘要： Compute engine circuitry configured to represent a spin network mapping of a graph representing a combinatorial optimization problem includes a plurality of ring oscillator cells, each of which includes a ring oscillator having an oscillator output, at least one coupling block, and a read block. Each coupling block connects the ring oscillator of the cell to the ring oscillator of one of a plurality of neighboring cells to form a coupled ring oscillator. The read block generates a state output for each coupled ring oscillator that indicates whether the coupled ring oscillator is in one of a same-phase state, in which the connected ring oscillators oscillate in phase with each other, and an opposite-phase state, in which the connected ring oscillators oscillate in an opposite phase from each other. A controller is configured to output a total energy of the mapping based on the state outputs.

38. 发明公开

US20230403865A1 SPIN LOGIC DEVICE BASED ON SPIN-CHARGE CONVERSION AND SPIN LOGIC ARRAY USING THE SAME 审中-公开
公开(公告)号：US20230403865A1
公开(公告)日：2023-12-14
申请号：US18455449
申请日：2023-08-24
申请人： INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY , INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
发明人： Jongill HONG , Saeroonter OH
IPC分类号： H10B61/00 , H03K19/17728 , H03K19/18 , H01F10/32 , H10N59/00 , H10N50/80 , H10N50/85
CPC分类号： H10B61/00 , H03K19/17728 , H03K19/18 , H01F10/3272 , H01F10/3286 , H01F10/3254 , H01F10/329 , H10N59/00 , H10N50/80 , H10N50/85
摘要： Disclosed are a spin logic device based on spin-charge conversion and a spin logic array using the same. A reconfigurable spin logic array according to an exemplary embodiment of the present invention may include: an input terminal receiving at least three current signals; a plurality of wires transmitting the current signal in connection with the input terminal and including a horizontal wire and a vertical wire which cross each other; a first gate array in which at least one first majority gate connected to the input terminal through the wires and implemented based on the spin logic device is arranged; and a second gate array in which at least one second majority gate connected to the first gate array through the wires and implemented based on the spin logic device is arranged.

39. 发明公开

US20230352109A1 CURRENT-DRIVEN MAGNETIC DOMAIN-WALL LOGIC 审中-公开
公开(公告)号：US20230352109A1
公开(公告)日：2023-11-02
申请号：US17909490
申请日：2021-01-26
申请人： Paul Scherrer Institut
发明人： Zhaochu Luo , Ales Hrabec , Laura J. Heyderman , Pietro Gambardella , Trong Phuong Dao
IPC分类号： G11C19/08 , H10N50/10 , G11C11/16 , H10N52/80 , H10N50/85 , H03K19/18
CPC分类号： G11C19/0841 , H10N50/10 , G11C11/161 , H10N52/80 , H10N50/85 , H03K19/18
摘要： A spin-based logic architecture provides nonvolatile data retention, near-zero leakage, and scalability. The architecture based on magnetic domain-walls take advantage of fast domain-wall motion, high density, non-volatility, and flexible design in order to process and store information. There is disclosed a concept to perform all-electric logic operations and cascading in domain-wall racetracks. The novel system exploits chiral coupling between neighboring magnetic domains induced by the interfacial Dzyaloshinskii-Moriya interaction to realize a domain-wall inverter. There are described reconfigurable NAND and NOR logic gates that perform operations with current-induced domain-wall motion. Several NAND gates are cascaded to build XOR and full adder gates, demonstrating electrical control of magnetic data and device interconnection in logic circuits. The novel system provides a viable platform for scalable all-electric magnetic logic and paves the way for memory-in-logic applications.

40. 发明授权

US11790966B2 Nonvolatile logic circuit 有权
公开(公告)号：US11790966B2
公开(公告)日：2023-10-17
申请号：US17417917
申请日：2019-11-28
申请人： TOHOKU UNIVERSITY
发明人： Masanori Natsui , Takahiro Hanyu , Tetsuo Endoh
IPC分类号： G11C11/16 , H03K19/18 , H10B61/00 , H10N50/80 , H03K19/20
CPC分类号： G11C11/161 , H03K19/18 , H10B61/00 , H10N50/80 , H03K19/20
摘要： A nonvolatile logic circuit includes: a memory unit having a pair of resistive memory elements; a computation unit connected to the memory unit and configured to perform an operation based on an input signal and a logic value corresponding to a resistance state of the pair of resistive memory elements; a determination circuit configured to determine whether the resistance state of the pair of resistive memory elements is a complementary state or a non-complementary state; and an output circuit connected to the computation unit and the determination circuit, and configured to output a signal corresponding to an operation result by the computation unit or a signal corresponding to a determination result by the determination circuit.

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