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31. 发明申请

US20100176441A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100176441A1
公开(公告)日：2010-07-15
申请号：US12663361
申请日：2008-06-06
申请人： Yoshihiro Hirota
发明人： Yoshihiro Hirota
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/022 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/02247 , H01L21/02252 , H01L21/02255 , H01L21/02274 , H01L21/3185 , H01L29/40117 , H01L29/42352 , H01L29/66833 , H01L29/7923
摘要： In a nonvolatile semiconductor memory device of the method which enables a single cell to store more than or equal to 2-bit information, it is possible to prevent wire failure and ensure high operation reliability. The nonvolatile semiconductor memory device 200 includes a trench 203 having a round wall portion 203b; a tunnel oxide film 205, silicon nitride films 207a and 207b as charge trapping regions, a silicon dioxide film 209, a gate electrode 211, and a first source/drain region 213a and a second source/drain region 213b formed on Si substrates 201 arranged to have the gate electrode 211 therebetween.
摘要翻译：在使得单个单元能够存储大于或等于2位信息的方法的非易失性半导体存储器件中，可以防止电线故障并确保高操作可靠性。非易失性半导体存储器件200包括具有圆壁部分203b的沟槽203; 隧道氧化膜205，作为电荷捕获区的氮化硅膜207a和207b，形成在Si衬底201上形成的二氧化硅膜209，栅电极211和第一源极/漏极区213a和第二源极/漏极区213b 使栅电极211在其间。

32. 发明授权

US07732855B2 Semiconductor memory device including recessed control gate electrode 失效
标题翻译：半导体存储器件包括凹入控制栅电极
公开(公告)号：US07732855B2
公开(公告)日：2010-06-08
申请号：US11808982
申请日：2007-06-14
申请人： Sang-jin Park , Kwang-soo Seol , Yoon-dong Park , Sang-min Shin , In-jun Hwang , Sang-moo Choi , Ju-hee Park
发明人： Sang-jin Park , Kwang-soo Seol , Yoon-dong Park , Sang-min Shin , In-jun Hwang , Sang-moo Choi , Ju-hee Park
IPC分类号： H01L21/28
CPC分类号： H01L29/42324 , G11C16/0408 , H01L21/28273 , H01L21/28282 , H01L29/42336 , H01L29/4234 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.
摘要翻译：半导体存储器件可以包括半导体衬底，至少一个控制栅电极，至少一个存储节点层，至少一个隧道绝缘层，至少一个阻挡绝缘层和/或第一和第二沟道区。至少一个控制栅电极可以凹进到半导体衬底中。所述至少一个存储节点层可以在所述至少一个控制栅电极的侧壁和所述半导体衬底之间。所述至少一个隧道绝缘层可以在所述至少一个存储节点层和所述至少一个控制栅电极之间。所述至少一个阻挡绝缘层可以在所述存储节点层和所述控制栅电极之间。第一和第二沟道区可以在至少一个隧道绝缘层和半导体衬底之间，以围绕控制栅电极的侧壁的至少一部分和/或可以彼此分离。

33. 发明授权

US07729164B2 Non-volatile memory device, method of operating the same, and method of fabricating the same 有权
标题翻译：非易失性存储器件，其操作方法及其制造方法
公开(公告)号：US07729164B2
公开(公告)日：2010-06-01
申请号：US12010943
申请日：2008-01-31
申请人： Suk-pil Kim , Yoon-dong Park , Deok-kee Kim , Won-joo Kim , Young-gu Jin , Seung-hoon Lee
发明人： Suk-pil Kim , Yoon-dong Park , Deok-kee Kim , Won-joo Kim , Young-gu Jin , Seung-hoon Lee
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L29/42328 , H01L29/42336 , H01L29/42344 , H01L29/42352 , H01L29/66825 , H01L29/66833
摘要： A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The plurality of charge storage layers may be between the plurality of control gate electrodes and the semiconductor layer. The first and second auxiliary electrodes may be arranged to face each other. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer.
摘要翻译：非易失性存储器件可以包括至少一个半导体层，多个控制栅电极，多个电荷存储层，至少一个第一辅助电极和/或至少一个第二辅助电极。多个控制栅电极可以凹入半导体层。多个电荷存储层可以在多个控制栅电极和半导体层之间。第一和第二辅助电极可以被布置成彼此面对。多个控制栅电极可以在第一和第二辅助电极之间并与半导体层电容耦合。

34. 发明申请

US20100019309A1 MULTI-LEVEL FLASH MEMORY STRUCTURE 审中-公开
标题翻译：多级闪存存储器结构
公开(公告)号：US20100019309A1
公开(公告)日：2010-01-28
申请号：US12178465
申请日：2008-07-23
申请人： LIH WEI LIN , WEI SHENG HSU
发明人： LIH WEI LIN , WEI SHENG HSU
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L29/40114 , H01L29/40117 , H01L29/42336 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/7887
摘要： A multi-level flash memory structure comprises a semiconductor substrate having a protrusion, a plurality of storage structures separated by the protrusion, a dielectric layer overlying the storage structures and the protrusion of the semiconductor substrate, a gate structure positioned on the dielectric layer, and several diffusion regions positioned at the sides of the protrusion. Each of the storage structures includes a charge-trapping site and an insulation structure isolating the charge-trapping site from the semiconductor substrate.
摘要翻译：多级闪速存储器结构包括具有突起的半导体衬底，由突起分开的多个存储结构，覆盖存储结构的覆盖层和半导体衬底的突起，位于介电层上的栅极结构，以及几个扩散区域位于突起的侧面。每个存储结构包括电荷捕获位点和将电荷捕获位点与半导体衬底隔离的绝缘结构。

35. 发明授权

US07626230B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07626230B2
公开(公告)日：2009-12-01
申请号：US11657650
申请日：2007-01-25
申请人： Kyung Joong Joo , Han Soo Kim
发明人： Kyung Joong Joo , Han Soo Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42336 , H01L29/42352
摘要： Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region.
摘要翻译：示例性实施例涉及制造半导体器件和半导体器件的方法，所述半导体器件和半导体器件包括：衬底，其包括多个有源区和相邻有源区之间的多个隔离区，每个有源区包括沟槽，凹槽的底面为在有源区的上表面下方。

36. 发明申请

US20090159961A1 SEMICONDUCTOR MEMORY DEVICE WITH STACKED GATE INCLUDING CHARGE STORAGE LAYER AND CONTROL GATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有包括充电储存层和控制栅的堆积门的半导体存储器件及其制造方法
公开(公告)号：US20090159961A1
公开(公告)日：2009-06-25
申请号：US12338417
申请日：2008-12-18
申请人： Yoshiko Kato , Mitsuhiro Noguchi
发明人： Yoshiko Kato , Mitsuhiro Noguchi
IPC分类号： H01L29/792 , H01L21/265
CPC分类号： H01L21/26586 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11568 , H01L27/11573 , H01L29/42336 , H01L29/42352 , H01L29/7881 , H01L29/792
摘要： A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region.
摘要翻译：半导体存储器件包括第一有源区，第二有源区，第一元件隔离区和第二元件隔离区。第一有源区形成在半导体衬底中。第二有源区形成在半导体衬底中。第一元件隔离区域使彼此相邻的第一有源区域电隔离。第二元件隔离区域将彼此相邻的第二有源区域电隔离。与第二元件隔离区域的侧面接触的第二有源区域的一部分中的杂质浓度高于第二有源区域的中心部分的杂质浓度，第一有源区域的一部分中的杂质浓度在与第一元件隔离区域的侧面的接触与第一有源区域中的相同。

37. 发明申请

US20090045454A1 Semiconductor non-volatile memory cell, method of producing the same, semiconductor non-volatile memory having the semiconductor non-volatile memory cell, and method of producing the same 有权
标题翻译：半导体非易失性存储单元及其制造方法，具有半导体非易失性存储单元的半导体非易失性存储器及其制造方法
公开(公告)号：US20090045454A1
公开(公告)日：2009-02-19
申请号：US12155983
申请日：2008-06-12
申请人： Koji Takaya , Akiyuki Minami
发明人： Koji Takaya , Akiyuki Minami
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/42352 , H01L29/785 , H01L29/7853 , H01L29/7923
摘要： A semiconductor non-volatile memory cell includes an Si (silicon) layer containing substrate including an activation region having a ridge portion; an element separation region embedded in both sides of the activation region; a gate electrode with a gate insulation film inbetween formed over the ridge portion for covering a part of both side surfaces of the ridge portion and an upper surface of the element separation region; a channel forming region formed in a surface layer region of the ridge portion; an extension region formed on both sides of the channel forming region in the longitudinal direction; and an electric charge accumulation layer capable of accumulating electric charges and a sidewall formed on the extension region and one or both of side surfaces of the gate electrode facing with each other in the longitudinal direction.
摘要翻译：半导体非易失性存储单元包括具有包含具有脊部分的激活区域的含Si（硅）层的衬底; 嵌入激活区域的两侧的元件分离区域; 在所述脊部上形成有栅极绝缘膜的栅电极，用于覆盖所述脊部的两个侧面的一部分和所述元件分离区域的上表面; 形成在所述脊部的表层区域中的沟道形成区域; 在纵向方向上形成在通道形成区域的两侧的延伸区域; 以及能够积聚电荷的电荷积累层和形成在所述延伸区域上的侧壁以及在所述栅极电极的侧表面中的一个或两个在所述纵向方向上彼此面对的电荷累积层。

38. 发明申请

US20090020799A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090020799A1
公开(公告)日：2009-01-22
申请号：US12005869
申请日：2007-12-28
申请人： Hiroyuki Nansei
发明人： Hiroyuki Nansei
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L29/42352 , H01L29/7881 , H01L29/792
摘要： One embodiment in accordance with the invention can include a semiconductor device that includes: a groove that is formed in a semiconductor substrate; bottom oxide films that are formed on both side faces of the groove; two charge storage layers that are formed on side faces of the bottom oxide films; top oxide films that are formed on side faces of the two charge storage layers; and a silicon oxide layer that is formed on the bottom face of the groove, and has a smaller film thickness than the top oxide films.
摘要翻译：根据本发明的一个实施例可以包括半导体器件，其包括：形成在半导体衬底中的沟槽; 形成在槽的两个侧面上的底部氧化物膜; 形成在底部氧化物膜的侧面上的两个电荷存储层; 形成在两个电荷存储层的侧面上的顶部氧化物膜; 以及形成在所述槽的底面上并且具有比所述顶部氧化物膜更薄的膜厚度的氧化硅层。

39. 发明授权

US07462529B2 Nonvolatile memory device for storing multi-bit data 有权
标题翻译：用于存储多位数据的非易失性存储器件
公开(公告)号：US07462529B2
公开(公告)日：2008-12-09
申请号：US11386686
申请日：2006-03-23
申请人： Tsutomu Nakai
发明人： Tsutomu Nakai
IPC分类号： H01L21/8238
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/42352 , H01L29/792 , H01L29/7923
摘要： A semiconductor nonvolatile memory device for storing multi-bit data has a memory cell having a source region S and a drain region D formed at the surface of a semiconductor substrate, a gate insulator film and a control gate CG formed on a channel region CH between the source region S and the drain region D and a nonconductive trap gate in the gate insulator film. An indentation is provided at the surface of the semiconductor substrate covering a region from a position in the vicinity of the drain region in the channel region to the drain region. By providing the indentation on the drain region side of the channel region, the trap gate is positioned in the direction of a channel current flowing from the source region S to the drain region D. Then, a charge having run through the channel region CH is injected efficiently into the trap gate on the indentation.
摘要翻译：用于存储多位数据的半导体非易失性存储器件具有存储单元，其具有形成在半导体衬底的表面处的源极区域S和漏极区域D，栅极绝缘膜和控制栅极CG，栅极绝缘膜和控制栅极CG形成在沟道区域CH之间，源极区S和漏极区D以及栅极绝缘膜中的非导电陷阱栅极。在半导体衬底的表面上设置有一个凹槽，该凹槽覆盖从沟道区域中的漏极区域附近的位置到漏极区域的区域。通过在沟道区域的漏极区侧设置凹陷，阱栅位于从源极区域S流到漏极区域D的沟道电流的方向上。然后，穿过沟道区域CH的电荷为有效地注入压痕中的陷阱门。

40. 发明申请

US20080258199A1 FLASH MEMORY DEVICE AND FABRICATING METHOD THEREOF 有权
标题翻译：闪存存储器件及其制造方法
公开(公告)号：US20080258199A1
公开(公告)日：2008-10-23
申请号：US11736114
申请日：2007-04-17
申请人： Jong-Ho Lee
发明人： Jong-Ho Lee
IPC分类号： H01L29/788 , H01L21/04
CPC分类号： H01L29/66833 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352 , H01L29/66825 , H01L29/785 , H01L29/7881 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： The present invention relates to a flash memory device and its fabrication method, in more detail, it relates to a novel device structure for improving a scaling-down characteristic/performance and increasing memory capacity of the MOS-based flash memory device.A new device structure according to the present invention is compatible with existing fabrication process and is based on a recessed channel, which is capable of easily implementing highly-integrated/high-performance and 2-bit/cell. The proposed device has a structure suppressing the short channel effect while largely reducing the cell area and enabling 2-bit/cell by forming the charge storage node as a spacer inside the recessed channel. Moreover, if selectively removing the dielectric films around the recessed silicon surface, the sides as well as the surface of the recessed channel is exposed. A spacer can be also made in this situation and used for a storage node, thereby improving the channel controllability of the control electrode and the on-off characteristic of a device. The proposed structure also takes advantage of resolving the threshold voltage problem and improving the write/erase speeds.
摘要翻译：本发明涉及闪速存储器件及其制造方法，更详细地说，涉及一种用于改善按比例缩小特性/性能并增加基于MOS的闪存器件的存储器容量的新型器件结构。根据本发明的新器件结构与现有制造工艺兼容，并且基于能够容易地实现高度集成/高性能和2位/单元的凹陷通道。所提出的装置具有抑制短信道效应的结构，同时通过在凹陷通道内形成作为间隔物的电荷存储节点，大大减小了单元面积并使得能够实现2位/单元。此外，如果选择性地去除凹陷硅表面周围的电介质膜，则侧面以及凹槽的表面被暴露。在这种情况下也可以制造间隔物，用于存储节点，从而提高控制电极的通道可控性和装置的开 - 关特性。所提出的结构还利用解决阈值电压问题并提高写/擦除速度。

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