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31. 发明授权

US07825461B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07825461B2
公开(公告)日：2010-11-02
申请号：US11798947
申请日：2007-05-18
申请人： Kyung Joong Joo , Han Soo Kim
发明人： Kyung Joong Joo , Han Soo Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42336 , H01L29/42352
摘要： Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region.
摘要翻译：示例性实施例涉及制造半导体器件和半导体器件的方法，所述半导体器件和半导体器件包括：衬底，其包括多个有源区和相邻有源区之间的多个隔离区，每个有源区包括沟槽，凹槽的底面为在有源区的上表面下方。

32. 发明授权

US07811890B2 Vertical channel transistor structure and manufacturing method thereof 有权
标题翻译：垂直沟道晶体管结构及其制造方法
公开(公告)号：US07811890B2
公开(公告)日：2010-10-12
申请号：US11545575
申请日：2006-10-11
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/42352
摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.
摘要翻译：提供了垂直沟道晶体管结构。该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。通道形成为从基板突出的鳍状结构。盖层沉积在鳍状结构上。盖层和鳍状结构具有基本上相同的宽度。电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。源极和漏极分别位于鳍状结构的两侧并与栅极相对。

33. 发明授权

US07787302B2 Flash memory device, method of manufacturing the same, and method of operating the same 失效
标题翻译：闪存装置及其制造方法及其操作方法
公开(公告)号：US07787302B2
公开(公告)日：2010-08-31
申请号：US12073681
申请日：2008-03-07
申请人： Sung-Il Park , Sung-Hoon Lee , Kwang-Soo Seol , Young-Gu Jin , Jong-Seob Kim
发明人： Sung-Il Park , Sung-Hoon Lee , Kwang-Soo Seol , Young-Gu Jin , Jong-Seob Kim
IPC分类号： G11C16/04
CPC分类号： H01L21/28282 , G11C16/349 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352 , H01L29/66833 , H01L29/792
摘要： Provided are a memory device, a method of manufacturing the same, and a method of operating the same. The memory device may include a channel region having an upper end where both sides of the upper end are curved, the curved portions of both sides allowing charges to be injected thereinto in a program or erase voltage such that the curved portions into which the charges are injected are separate from a portion which determines a threshold voltage, and a gate structure on the channel region.
摘要翻译：提供了一种存储器件及其制造方法及其操作方法。存储器件可以包括具有上端的上端弯曲的上端的通道区域，两侧的弯曲部分允许以编程或擦除电压将电荷注入其中，使得电荷的弯曲部分注入与确定阈值电压的部分和沟道区上的栅极结构分开。

34. 发明申请

US20100193857A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100193857A1
公开(公告)日：2010-08-05
申请号：US12698533
申请日：2010-02-02
申请人： Kenichiro NAKAGAWA
发明人： Kenichiro NAKAGAWA
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11521 , H01L29/42344 , H01L29/42352 , H01L29/7851
摘要： A split gate type nonvolatile semiconductor memory device having a FinFET structure includes a semiconductor substrate, parallel trenches on a surface of the semiconductor substrate, and select and memory gate electrodes perpendicular to the trenches. While either the select or the memory gate electrodes are formed prior to the other gate electrodes, each remaining gate electrode is formed adjacent to a side wall of each of the gate electrodes. The semiconductor memory device includes source/drain regions each formed between each pair of the select gate electrodes and between each pair of the memory gate electrodes in protruding portions between each pair of the trenches. A difference between heights of the select gate electrodes and the memory gate electrodes is equal to or greater than a difference between heights of insulation layers formed on the bottom of each of the trenches and the source/drain regions.
摘要翻译：具有FinFET结构的分离栅型非易失性半导体存储器件包括半导体衬底，在半导体衬底的表面上的平行沟槽，以及垂直于沟槽的选择存储栅电极。虽然选择栅极电极或存储器栅电极在其它栅电极之前形成，但是每个剩余的栅极电极邻近每个栅电极的侧壁形成。半导体存储器件包括在每对选择栅极电极之间形成的源极/漏极区域和在每对沟槽之间的突出部分中的每对存储栅电极之间。选择栅电极和存储栅电极的高度之间的差异等于或大于形成在每个沟槽和源极/漏极区域的底部上的绝缘层的高度差。

35. 发明申请

US20100109073A1 FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：闪存存储器件及其制造方法
公开(公告)号：US20100109073A1
公开(公告)日：2010-05-06
申请号：US12604665
申请日：2009-10-23
申请人： Jin-Ha Park
发明人： Jin-Ha Park
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11568 , H01L29/40117 , H01L29/42352 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A flash memory device includes a semiconductor substrate having a trench formed therein, the trench including a device isolation film, an oxide film formed over the semiconductor substrate including the trench, a nitride film pattern inserted into the oxide film and formed at a sidewall of the trench, and a polysilicon pattern formed over the oxide film including the nitride film pattern. A method for manufacturing a flash memory device includes forming a first oxide film over the semiconductor substrate including the trench, forming the nitride film pattern at the sidewall of the trench provided with the first oxide film and forming a second oxide film over the semiconductor substrate including the nitride film pattern, forming an oxide film pattern at a contact surface between the nitride film pattern and the semiconductor substrate and a side of the nitride film pattern by partially removing the first oxide film and the second oxide film formed over the bottom of the trench and the semiconductor substrate, and forming a third oxide film over the semiconductor substrate including the oxide film pattern to form the oxide cover film into which the nitride film pattern is inserted.
摘要翻译：闪速存储器件包括其中形成有沟槽的半导体衬底，沟槽包括器件隔离膜，形成在包括沟槽的半导体衬底上的氧化膜，氮化物膜图案插入到氧化物膜中并形成在沟槽，以及在包括氮化物膜图案的氧化物膜上形成的多晶硅图案。一种闪速存储器件的制造方法包括：在包括沟槽的半导体衬底上形成第一氧化膜，在设置有第一氧化膜的沟槽的侧壁处形成氮化物膜图案，并在半导体衬底上形成第二氧化膜，包括：氮化物膜图案，通过部分去除在沟槽的底部形成的第一氧化物膜和第二氧化物膜，在氮化物膜图案和半导体衬底之间的接触表面和氮化物膜图案的一侧上形成氧化膜图案和半导体衬底，并且在包括氧化物膜图案的半导体衬底上形成第三氧化物膜，以形成其中插入氮化物膜图案的氧化物覆盖膜。

36. 发明申请

US20100090257A1 SEMICONDUCTOR DEVICE, AND ITS MANUFACTURING METHOD 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100090257A1
公开(公告)日：2010-04-15
申请号：US12447113
申请日：2007-10-23
申请人： Masayuki Terai , Shinji Fujieda , Akio Toda
发明人： Masayuki Terai , Shinji Fujieda , Akio Toda
IPC分类号： H01L29/04 , H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L27/11565 , H01L27/11568 , H01L29/42344 , H01L29/42348 , H01L29/42352 , H01L29/66833 , H01L29/7923 , H01L29/7926
摘要： A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.
摘要翻译：在基板的凹部或突出部形成沟道，并且形成栅极绝缘膜，以沿着沟道具有第一至第三绝缘区域。第一绝缘区域和第三绝缘区域的每个栅极绝缘膜具有不包含形成在不同于基板的主面的平面上的电荷阱的第一栅极绝缘膜，含有电荷阱的电荷积累膜，以及不含电荷陷阱的第二栅绝缘膜。中间的第二绝缘区域的栅极绝缘膜形成在与基板的主表面平行的平面上，并且仅由不含电荷陷阱的第三栅极绝缘膜构成。

37. 发明申请

US20100008143A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF 失效
标题翻译：非易失性半导体存储器件及其控制方法
公开(公告)号：US20100008143A1
公开(公告)日：2010-01-14
申请号：US12475799
申请日：2009-06-01
申请人： Akira Umezawa
发明人： Akira Umezawa
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/10 , G11C16/0466 , H01L21/28282 , H01L27/11568 , H01L29/42352 , H01L29/66833 , H01L29/792
摘要： A nonvolatile semiconductor memory device includes a multi-layer insulating film having at least charge storage layers and formed on bottom surfaces and both side surfaces of a plurality of trench portions respectively formed in portions between the plurality of active areas formed in a first direction, a plurality of gate electrodes filled in internal portions of the plurality of trench portions with the multi-layer insulating film, a plurality of first metal interconnections formed in a second direction and each functioning as a bit line or source line, and a plurality of first conductivity-type diffusion layer regions arranged in a staggered form in corresponding portions of the plurality of active areas which intersect with the plurality of first metal interconnections. The device further includes a plurality of connection contacts form to respectively connect the plurality of first conductivity-type diffusion layer regions to the plurality of first metal interconnections.
摘要翻译：非易失性半导体存储器件包括至少具有电荷存储层并且形成在分别形成在沿第一方向形成的多个有源区域之间的部分中的多个沟槽部分的底表面和两个侧表面上的多层绝缘膜，多个栅电极，多个沟槽部的内部被多层绝缘膜填充，多个第一金属互连形成在第二方向上，并且各自作为位线或源极线，以及多个第一导电性型扩散层区域以交错的形式布置在与多个第一金属互连相交的多个有效区域的对应部分中。该装置还包括多个连接触头形式，以将多个第一导电类型扩散层区域分别连接到多个第一金属互连。

38. 发明申请

US20100006914A1 Nonvolatile semiconductor memory device, and method for manufacturing nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件以及用于制造非易失性半导体存储器件的方法
公开(公告)号：US20100006914A1
公开(公告)日：2010-01-14
申请号：US12458339
申请日：2009-07-08
申请人： Kenichiro Nakagawa
发明人： Kenichiro Nakagawa
IPC分类号： H01L29/68 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11565 , H01L27/11568 , H01L29/42344 , H01L29/42352 , H01L29/7926
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate that includes a trench, a charge storage layer that is formed inside of the trench, a first gate that is formed above a side surface and a bottom surface of the trench, a second gate that is formed beside the first gate, and that is formed above the charge storage layer, a first diffusion region that is formed on the semiconductor substrate inside of the trench, and a second diffusion region that is formed on the semiconductor substrate outside of the trench.
摘要翻译：非易失性半导体存储器件包括半导体衬底，其包括沟槽，形成在沟槽内部的电荷存储层，形成在沟槽的侧表面和底表面之上的第一栅极，形成的第二栅极在第一栅极旁边，形成在电荷存储层的上方，形成在沟槽的内部的半导体基板上的第一扩散区域和形成在沟槽的外部的半导体基板上的第二扩散区域。

39. 发明申请

US20090158234A1 VERTICAL SOI TRENCH SONOS CELL 有权
标题翻译：垂直SOI TRENCH SONOS电池
公开(公告)号：US20090158234A1
公开(公告)日：2009-06-18
申请号：US11955913
申请日：2007-12-13
申请人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
发明人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
IPC分类号： G06F17/50
CPC分类号： H01L29/42352 , H01L21/28282 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/66833
摘要： A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.
摘要翻译：提供半导体存储器件和包括体现在机器可读介质中的半导体存储器件的设计结构。特别地，本发明包括其中在绝缘体上半导体（SOI）衬底中产生垂直沟槽半导体 - 氧化物 - 氮化物 - 氧化物 - 半导体（SONOS）存储单元的半导体存储器件，其允许将基于SOI的互补金属氧化物半导体（CMOS）技术中的致密非易失性随机存取存储器（NVRAM）单元。使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

40. 发明授权

US07480185B2 Ballistic injection NROM flash memory 有权
标题翻译：弹道注射NROM闪存
公开(公告)号：US07480185B2
公开(公告)日：2009-01-20
申请号：US11691603
申请日：2007-03-27
申请人： Leonard Forbes
发明人： Leonard Forbes
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/26 , H01L21/28282 , H01L29/42348 , H01L29/42352 , H01L29/7923
摘要： A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride storage regions are isolated from each other by a depression in the control gate. In a vertical embodiment, the split nitride storage regions are separated by an oxide pillar. The cell is programmed by creating a positive charge on the nitride storage regions and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the nitride storage region that is adjacent to the pinched off channel region.
摘要翻译：分离式NROM闪存单元由衬底中的源/漏区组成。分裂的氮化物电荷存储区域通过第一氧化物层与衬底绝缘，并且通过第二层氧化物材料从控制栅极绝缘。氮化物存储区域通过控制栅极中的凹陷彼此隔离。在垂直实施例中，裂缝氮化物存储区域被氧化物柱分离。通过在氮化物存储区域上产生正电荷并在对源极区域接地的同时偏置漏极区域来对单元进行编程。这在漏极区域附近产生虚拟源极/漏极区域，使得热电子在狭窄的夹持区域中被加速。电子变成弹道，并且直接注入到与夹持的沟道区相邻的氮化物存储区上。

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