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31. 发明申请

US20140291762A1 POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE 有权
公开(公告)号：US20140291762A1
公开(公告)日：2014-10-02
申请号：US14305632
申请日：2014-06-16
申请人： IO Semiconductor Inc.
发明人： Jacek Korec , Boyi Yang
IPC分类号： H01L29/872 , H01L29/78
CPC分类号： H01L29/0626 , H01L21/823437 , H01L21/8249 , H01L27/0629 , H01L27/0635 , H01L27/088 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/41766 , H01L29/42304 , H01L29/4236 , H01L29/4933 , H01L29/66181 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66704 , H01L29/7302 , H01L29/735 , H01L29/78 , H01L29/7821 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/8605 , H01L29/861 , H01L29/872 , H01L29/94 , H01L2224/0401 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/11 , H01L2224/13 , H01L2924/00 , H01L2924/00014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091
摘要： A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

32. 发明授权

US08785278B2 Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact 有权
标题翻译：具有沟槽底部氧化物屏蔽和三维P体接触的纳米MOSFET
公开(公告)号：US08785278B2
公开(公告)日：2014-07-22
申请号：US13364948
申请日：2012-02-02
申请人： Hamza Yilmaz , Daniel Ng , Daniel Calafut , Madhur Bobde , Anup Bhalla , Ji Pan , Yeeheng Lee , Jongoh Kim
发明人： Hamza Yilmaz , Daniel Ng , Daniel Calafut , Madhur Bobde , Anup Bhalla , Ji Pan , Yeeheng Lee , Jongoh Kim
IPC分类号： H01L21/331
CPC分类号： H01L29/7813 , H01L21/26586 , H01L27/088 , H01L29/0623 , H01L29/0626 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.
摘要翻译：半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。在轻掺杂层中形成一个或多个器件。每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。体区与轻掺杂层和重掺杂层具有相反的导电类型。源区域靠近上表面形成。在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

33. 发明申请

US20140191309A1 VERTICAL POWER MOSFET 有权
标题翻译：垂直功率MOSFET
公开(公告)号：US20140191309A1
公开(公告)日：2014-07-10
申请号：US14109208
申请日：2013-12-17
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Satoshi EGUCHI , Yoshito NAKAZAWA , Tomohiro TAMAKI
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L29/0619 , H01L29/0626 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/0886 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/66727 , H01L29/7802 , H01L29/7811
摘要： When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to prevent a reduction in breakdown voltage due to fluctuations in concentration in an embedded epitaxial layer. However, according to the examination by the present inventors, it has been made clear that such a method makes design more and more difficult in response to the higher breakdown voltage. In the present invention, the concentration in an intermediate substrate epitaxy column area in each substrate epitaxy column area configuring a super junction is made more than that in other areas within the substrate epitaxy column area, in a vertical power MOSFET having the super junction by the embedded epitaxial method.
摘要翻译：当通过嵌入式外延法形成超级结时，通常在沟槽形成蚀刻中进行干蚀刻的锥角调整以形成倾斜的列，以便防止由嵌入的外延层中的浓度波动引起的击穿电压的降低。然而，根据本发明人的考察，已经清楚的是，这种方法使得设计越来越难以响应较高的击穿电压。在本发明中，在构成超结的每个衬底外延柱区域中的中间衬底外延柱区域中的浓度比在衬底外延柱区域内的其它区域的浓度高，嵌入式外延法。

34. 发明授权

US08686515B2 Double-groove bidirectional vertical component 有权
标题翻译：双槽双向垂直分量
公开(公告)号：US08686515B2
公开(公告)日：2014-04-01
申请号：US13332404
申请日：2011-12-21
申请人： Yannick Hague , Samuel Menard
发明人： Yannick Hague , Samuel Menard
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/87 , H01L29/0626 , H01L29/0638 , H01L29/0661 , H01L29/66121 , H01L29/66386 , H01L29/747
摘要： A mesa-type bidirectional vertical power component, including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; first regions of the first conductivity type in each of the layers of the second conductivity type; and, at the periphery of each of its surfaces, two successive grooves, the internal groove crossing the layers of the second conductivity type, second doped regions of the first conductivity type being formed under the surface of the external grooves and having the same doping profile as the first regions.
摘要翻译：一种台面型双向垂直功率元件，包括第一导电类型的衬底; 在基板的每一侧上具有第二导电类型的层; 在第二导电类型的每个层中的第一导电类型的第一区域; 并且在其每个表面的周边处，两个连续的凹槽，与第二导电类型的层交叉的内部沟槽，第一导电类型的第二掺杂区域形成在外部沟槽的表面下方并且具有相同的掺杂分布作为第一个地区。

35. 发明申请

US20140048872A1 AVALANCHE CAPABILITY IMPROVEMENT IN POWER SEMICONDUCTOR DEVICES USING THREE MASKS PROCESS 有权
标题翻译：使用三个掩码过程的功率半导体器件中的AVALANCHE性能改进
公开(公告)号：US20140048872A1
公开(公告)日：2014-02-20
申请号：US13949357
申请日：2013-07-24
申请人： Force Mos Technology Co., Ltd.
发明人： FU-YUAN HSIEH
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , H01L29/0626 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7808 , H01L29/7813
摘要： A power semiconductor device with improved avalanche capability is disclosed by forming at least one avalanche capability enhancement doped region underneath an ohmic contact doped region. Moreover, a source mask is saved by using three masks process and the avalanche capability is further improved.
摘要翻译：通过在欧姆接触掺杂区域下方形成至少一个雪崩能力增强掺杂区域来公开具有改进的雪崩能力的功率半导体器件。此外，通过使用三个掩模处理来保存源掩码，并且进一步改进雪崩能力。

36. 发明授权

US08647950B2 Vertical gate LDMOS device 有权
标题翻译：垂直门LDMOS器件
公开(公告)号：US08647950B2
公开(公告)日：2014-02-11
申请号：US13572428
申请日：2012-08-10
申请人： Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
发明人： Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
IPC分类号： H01L21/336
CPC分类号： H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要： A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.
摘要翻译：一种在LDMOS晶体管中制造垂直栅极区域的方法，包括在植入在衬底上的n阱区域上沉积第一掩模层，图案化第一掩模层以限定区域，在该区域上沉积第二掩模层，在所述区域的第一部分中的第二掩模层以暴露所述n阱区域，以及蚀刻所暴露的n阱区域以形成第一沟槽。从n阱区域的表面延伸到第一深度的第一沟槽被填充有氧化物。在该区域的第二部分中蚀刻第二掩模层以暴露n阱区域。在n阱中形成第二沟槽，第二沟槽从表面延伸到第二深度，小于第一深度。通过用导电材料填充第二沟槽来形成非对称垂直栅极。

37. 发明申请

US20130299835A1 Semiconductor Device with an Integrated Poly-Diode 有权
标题翻译：具有集成多极管的半导体器件
公开(公告)号：US20130299835A1
公开(公告)日：2013-11-14
申请号：US13849825
申请日：2013-03-25
申请人： Infineon Technologies Austria AG
发明人： Franz Hirler , Anton Mauder , Frank Pfirsch , Hans-Joachim Schulze
IPC分类号： H01L29/739
CPC分类号： H01L29/66143 , H01L21/823487 , H01L29/0626 , H01L29/1095 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/6609 , H01L29/6634 , H01L29/66348 , H01L29/66727 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7813
摘要： A field effect semiconductor device includes a semiconductor body having a main horizontal surface and a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged between the first semiconductor region and the main horizontal surface, an insulating layer arranged on the main horizontal surface, and a first metallization arranged on the insulating layer. The first and second semiconductor regions form a pn-junction. The semiconductor body further has a deep trench extending from the main horizontal surface vertically below the pn-junction and including a conductive region insulated from the first semiconductor region and the second semiconductor region, and a narrow trench including a polycrystalline semiconductor region extending from the first metallization, through the insulating layer and at least to the conductive region. A vertical poly-diode structure including a horizontally extending pn-junction is arranged at least partly in the narrow trench.
摘要翻译：场效应半导体器件包括具有主水平表面和第一导电类型的第一半导体区域的半导体本体，布置在第一半导体区域和主水平表面之间的第二导电类型的第二半导体区域，布置成在主水平表面上，以及布置在绝缘层上的第一金属化。第一和第二半导体区域形成pn结。半导体本体还具有从垂直于pn结的下方的主水平表面延伸的深沟槽，并且包括与第一半导体区域和第二半导体区域绝缘的导电区域，以及包括从第一半导体区域延伸的多晶半导体区域的窄沟槽通过绝缘层和至少导电区域进行金属化。包括水平延伸的pn结的垂直多极二极管结构至少部分地布置在窄沟槽中。

38. 发明申请

US20130264636A1 Trench FET with Ruggedness Enhancement Regions 有权
标题翻译：具有坚固性增强区域的沟槽FET
公开(公告)号：US20130264636A1
公开(公告)日：2013-10-10
申请号：US13793926
申请日：2013-03-11
申请人： INTERNATIONAL RECTIFIER CORPORATION
发明人： Ashita Mirchandani , Timothy D. Henson , Ling Ma , Niraj Ranjan
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0626 , H01L29/0696 , H01L29/1095 , H01L29/41766
摘要： According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches.
摘要翻译：根据示例性实施方式，场效应晶体管（FET）包括延伸到第一导电类型的漂移区的第一和第二栅极沟槽。 FET还包括位于第一和第二栅极沟槽之间的第二导电类型的基极区域。坚固性增强区域位于第一和第二栅极沟槽之间，其中坚固性增强区域被配置为当FET处于雪崩状态时提供从漏极区域到基极区域的增强的雪崩电流路径。增强的雪崩电流路径远离第一和第二栅极沟槽。粗糙度增强区域可以是包括比基底区域更高的掺杂剂浓度的第二导电类型。此外，粗糙度增强区域可以在第一和第二栅极沟槽的下方延伸。

39. 发明申请

US20130256786A1 TRENCH MOSFET WITH SHIELDED ELECTRODE AND AVALANCHE ENHANCEMENT REGION 审中-公开
标题翻译：具有屏蔽电极和AVALANCHE增强区域的TRENCH MOSFET
公开(公告)号：US20130256786A1
公开(公告)日：2013-10-03
申请号：US13433627
申请日：2012-03-29
申请人： Fu-Yuan HSIEH
发明人： Fu-Yuan HSIEH
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0626 , H01L29/086 , H01L29/0869 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A trench MOSFET with shielded electrode and improved avalanche enhancement region is disclosed. The inventive structure can achieve a better avalanche capability by applying an improved avalanche enhancement region having a same doping concentration as the epitaxial layer where said trench MOSFET is formed without increasing Rds.
摘要翻译：公开了具有屏蔽电极和改进的雪崩增强区域的沟槽MOSFET。本发明的结构可以通过施加具有与形成所述沟槽MOSFET的外延层相同的掺杂浓度而不增加Rds的改进的雪崩增强区域来实现更好的雪崩能力。

40. 发明申请

US20130115744A1 Vertical Gate LDMOS Device 有权
标题翻译：垂直门LDMOS器件
公开(公告)号：US20130115744A1
公开(公告)日：2013-05-09
申请号：US13572428
申请日：2012-08-10
申请人： Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
发明人： Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan
IPC分类号： H01L29/66
CPC分类号： H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要： A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.
摘要翻译：一种在LDMOS晶体管中制造垂直栅极区域的方法，包括在植入在衬底上的n阱区域上沉积第一掩模层，图案化第一掩模层以限定区域，在该区域上沉积第二掩模层，在所述区域的第一部分中的第二掩模层以暴露所述n阱区域，以及蚀刻所暴露的n阱区域以形成第一沟槽。从n阱区域的表面延伸到第一深度的第一沟槽被填充有氧化物。在该区域的第二部分中蚀刻第二掩模层以暴露n阱区域。在n阱中形成第二沟槽，第二沟槽从表面延伸到第二深度，小于第一深度。通过用导电材料填充第二沟槽来形成非对称垂直栅极。

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