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31. 发明申请

US20080132021A1 High Performance FET Devices and Methods Thereof 有权
公开(公告)号：US20080132021A1
公开(公告)日：2008-06-05
申请号：US11971392
申请日：2008-01-09
申请人： Jack Oon Chu
发明人： Jack Oon Chu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/2807 , H01L21/28255 , H01L29/1029 , H01L29/1054 , H01L29/161 , H01L29/41783 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/4966 , H01L29/66628 , H01L29/66795 , H01L29/778 , H01L29/7787 , H01L29/7842 , H01L29/78642 , H01L29/78648 , H01L29/78684 , H01L29/78696
摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

32. 发明申请

US20070235759A1 CMOS process with Si gates for nFETs and SiGe gates for pFETs 审中-公开
标题翻译：用于nFET的Si栅极的CMOS工艺和用于pFET的SiGe栅极
公开(公告)号：US20070235759A1
公开(公告)日：2007-10-11
申请号：US11401672
申请日：2006-04-11
申请人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
发明人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
IPC分类号： H01L31/00
CPC分类号： H01L21/2807 , H01L21/823842
摘要： An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.
摘要翻译：提供了用于在同一半导体衬底上为pFET器件提供nFET器件的Si栅极和SiGe栅极的集成方案。该集成方案包括首先提供材料堆叠，其从底部到顶部包括在半导体衬底的表面上的栅极电介质，Si膜和硬掩模，其包括至少一个nFET器件区域和至少一个pFET器件区域。接下来，将硬掩模从至少一个pFET器件区域中的材料堆叠中选择性地去除，从而暴露Si膜。暴露的Si膜然后被转换成SiGe膜，此后在至少一个nFET器件区域中形成至少一个nFET器件，并且在至少一个pFET器件区域中形成至少一个pFET器件。根据本发明，至少一个nFET器件包括Si栅极，并且至少一个pFET包括SiGe栅极。

33. 发明申请

US20070099428A1 Plasma for patterning advanced gate stacks 审中-公开
标题翻译：等离子体用于图案化先进的栅极堆叠
公开(公告)号：US20070099428A1
公开(公告)日：2007-05-03
申请号：US11544351
申请日：2006-10-05
申请人： Denis Shamiryan , Vasile Paraschiv , Marc Demand , Werner Boullart
发明人： Denis Shamiryan , Vasile Paraschiv , Marc Demand , Werner Boullart
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32136 , H01L21/2807 , H01L21/28088 , H01L21/31122 , H01L29/513 , H01L29/517 , H01L29/78
摘要： A plasma composition and its use in a method for the dry etching of a stack of at least one material chemically too reactive towards the use of a Cl-based plasma are provided. Small amounts of nitrogen (5% up to 10%) can be added to a BCl3 comprising plasma and used in an anisotropical dry etching method whereby a passivation film is deposited onto the vertical sidewalls of stack etched for protecting the vertical sidewalls from lateral attack such that straight profiles can be obtained.
摘要翻译：提供了一种等离子体组合物及其在用于干法蚀刻至少一种对使用Cl基等离子体具有反应性的化学物质的堆叠的方法中的用途。可以将少量氮（5％至10％）加入到包含等离子体的BCl 3 3中，并用于各向异性热蚀干蚀刻方法中，由此钝化膜沉积在蚀刻的堆叠的垂直侧壁上保护垂直侧壁免受横向攻击，从而可以获得直线轮廓。

34. 发明申请

US20070048984A1 Metal work function adjustment by ion implantation 审中-公开
标题翻译：离子注入金属功函数调整
公开(公告)号：US20070048984A1
公开(公告)日：2007-03-01
申请号：US11217699
申请日：2005-08-31
申请人： Steven Walther , Ukyo Jeong , Sandeep Mehta , Naushad Variam
发明人： Steven Walther , Ukyo Jeong , Sandeep Mehta , Naushad Variam
IPC分类号： H01L21/425
CPC分类号： H01L21/28088 , H01L21/2807 , H01L21/28079 , H01L21/3215 , H01L22/14 , H01L29/495 , H01L29/4966
摘要： A system, method and program product for adjusting metal work function by ion implantation is disclosed. The invention determines the work function of the metal and determines a desired work function threshold for the metal. The desired work function threshold may be a range and is usually based on the work function of the substrate. An ion implanter system is then used to implant ions to at least a portion of the metal. The ion implantation is usually a high-energy ion stream including a material that is calculated to modify the work function of the metal. The ion implanter system continues to transmit the ion stream into the metal until the work function of the metal meets the desired work function threshold.
摘要翻译：公开了一种通过离子注入来调节金属功函数的系统，方法和程序产品。本发明确定金属的功函数并确定金属的期望功函数阈值。期望的功函数阈值可以是范围，并且通常基于衬底的功函数。然后使用离子注入机系统将离子注入金属的至少一部分。离子注入通常是高能离子流，其包括被计算以改变金属的功函数的材料。离子注入机系统继续将离子流传输到金属中，直到金属的功函数满足期望的功函数阈值。

35. 发明授权

US07129563B2 Method of fabricating a semiconductor device comprising a gate dielectric made of high dielectric permittivity material 有权
标题翻译：制造包括由高介电常数材料制成的栅极电介质的半导体器件的方法
公开(公告)号：US07129563B2
公开(公告)日：2006-10-31
申请号：US10815473
申请日：2004-04-01
申请人： Vincent Cosnier , Yves Morand , Olivier Kermarrec , Daniel Bensahel , Yves Campidelli
发明人： Vincent Cosnier , Yves Morand , Olivier Kermarrec , Daniel Bensahel , Yves Campidelli
IPC分类号： H01L31/0256
CPC分类号： H01L21/28185 , H01L21/2807 , H01L21/28194 , H01L29/4925 , H01L29/51 , H01L29/517
摘要： A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of Si1−xGex, where 0.5
摘要翻译：用于制造具有由高k材料制成的栅极电介质的半导体器件的工艺和器件包括直接在栅极电介质上沉积第一层Si 1-x Ge的步骤，在基本上低于通过热化学气相沉积（CVD）沉积多晶硅的温度的温度下，其中0.5

36. 发明授权

US07091135B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07091135B2
公开(公告)日：2006-08-15
申请号：US10798337
申请日：2004-03-12
申请人： Seiji Inumiya , Kazuhiro Eguchi
发明人： Seiji Inumiya , Kazuhiro Eguchi
IPC分类号： H01L21/31
CPC分类号： H01L21/28202 , H01L21/2807 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： There is disclosed a method of manufacturing a semiconductor device, which comprises forming a film containing metal elements and silicon elements on a semiconductor substrate, exposing the semiconductor substrate to an atmosphere containing an oxidant to form a silicon dioxide film at the interface between the semiconductor substrate and the film containing metal elements and silicon elements, and nitriding the film containing metal elements and silicon elements after forming the silicon dioxide film.
摘要翻译：公开了一种制造半导体器件的方法，其包括在半导体衬底上形成含有金属元素和硅元素的膜，将半导体衬底暴露于含有氧化剂的气氛中，以在半导体衬底之间的界面处形成二氧化硅膜并且所述膜含有金属元素和硅元素，并且在形成二氧化硅膜之后氮化包含金属元素和硅元素的膜。

37. 发明申请

US20060138555A1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060138555A1
公开(公告)日：2006-06-29
申请号：US11269543
申请日：2005-11-09
申请人： Kiyotaka Miyano
发明人： Kiyotaka Miyano
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/2807 , H01L21/823842 , H01L21/823857 , H01L29/49 , H01L29/665
摘要： According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising: forming a gate insulating film on a semiconductor substrate; forming a film containing a predetermined semiconductor material and germanium on the gate insulating film; oxidizing the film to form a first film having a germanium concentration higher than that of the film and a film thickness smaller than that of the film on the gate insulating film, and form an oxide film on the first film; removing the oxide film; forming, on the first film, a second film containing the semiconductor material and having a germanium concentration lower than that of the first film; forming a gate electrode by etching the second and first films; and forming a source region and drain region by ion-implanting a predetermined impurity by using the gate electrode as a mask.
摘要翻译：根据本发明的一个方面，提供一种半导体器件制造方法，包括：在半导体衬底上形成栅极绝缘膜; 在所述栅极绝缘膜上形成含有预定的半导体材料和锗的膜; 氧化膜以形成锗浓度高于膜的锗浓度并且膜厚小于栅极绝缘膜上的膜的膜厚度，并在第一膜上形成氧化物膜; 去除氧化膜; 在第一膜上形成含有半导体材料并且锗浓度低于第一膜的第二膜的第二膜; 通过蚀刻第二和第一膜形成栅电极; 以及通过使用栅极电极作为掩模，通过离子注入预定杂质来形成源区和漏区。

38. 发明申请

US20060054961A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060054961A1
公开(公告)日：2006-03-16
申请号：US11176271
申请日：2005-07-08
申请人： Masamichi Suzuki , Daisuke Matsushita , Takeshi Yamaguchi
发明人： Masamichi Suzuki , Daisuke Matsushita , Takeshi Yamaguchi
IPC分类号： H01L29/94
CPC分类号： H01L29/517 , H01L21/2807 , H01L21/28194 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/513
摘要： A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer containing La and Al, the metal oxide layer being provided at at least one of an interface between the silicon substrate and the insulation layer and an interface between the insulation layer and the electrode.
摘要翻译：半导体器件包括硅衬底; 形成在所述硅基板上的绝缘层，所述绝缘层含有至少一种选自Hf，Zr，Ti和Ta中的至少一种元素的氧化物; 形成在所述绝缘层上的电极; 以及包含La和Al的金属氧化物层，所述金属氧化物层设置在所述硅衬底和所述绝缘层之间的界面中的至少一个以及所述绝缘层和所述电极之间的界面。

39. 发明申请

US20060019466A1 Germanium substrate-type materials and approach therefor 有权
公开(公告)号：US20060019466A1
公开(公告)日：2006-01-26
申请号：US11188140
申请日：2005-07-22
申请人： Ammar Nayfeh , Chi On Chui , Krishna Saraswat , Takao Yonehara
发明人： Ammar Nayfeh , Chi On Chui , Krishna Saraswat , Takao Yonehara
IPC分类号： H01L21/30
CPC分类号： H01L29/518 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02587 , H01L21/0262 , H01L21/2807 , H01L21/28255 , H01L29/16 , H01L29/165 , H01L29/513 , H01L29/66575 , H01L29/94
摘要： Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.

40. 发明授权

US06969870B2 Semiconductor device having an amorphous silicon-germanium gate electrode 失效
标题翻译：具有非晶硅 - 锗栅电极的半导体器件
公开(公告)号：US06969870B2
公开(公告)日：2005-11-29
申请号：US10769863
申请日：2004-02-03
申请人： Hiroko Kubo , Kenji Yoneda
发明人： Hiroko Kubo , Kenji Yoneda
IPC分类号： H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78 , H01L29/04
CPC分类号： H01L29/49 , H01L21/2807 , H01L21/823842
摘要： A silicon germanium layer is deposited over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, an upper silicon layer in an amorphous state is deposited on the silicon germanium layer. Thereafter, a gate electrode is formed by patterning the silicon germanium layer and the upper silicon layer.
摘要翻译：在半导体衬底上沉积硅锗层，其中栅极绝缘膜置于衬底和硅锗层之间。然后，将非晶态的上硅层沉积在硅锗层上。此后，通过图案化硅锗层和上硅层形成栅电极。

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