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31. 发明申请

US20170103024A1 INFORMATION PROCESSING APPARATUS AND CACHE CONTROL METHOD 审中-公开
公开(公告)号：US20170103024A1
公开(公告)日：2017-04-13
申请号：US15263452
申请日：2016-09-13
申请人： FUJITSU LIMITED
发明人： Yuki MATSUO
IPC分类号： G06F12/123 , G06F12/0862 , G06F12/0893
CPC分类号： G06F12/123 , G06F12/0862 , G06F12/121 , G06F2212/1021 , G06F2212/602 , G06F2212/6026
摘要： A processor generates stream information indicating a stream of access events, based on a positional relationship between a plurality of first data blocks that are accessed in a storage device. The processor monitors access to a plurality of second data blocks that are prefetched based on the stream information, and determines whether the stream is ended based on elapsed time from last access to any of the plurality of second data blocks. The processor removes at least one of the plurality of second data blocks from the memory when the stream is determined to be ended.

32. 发明授权

US09612963B2 Store forwarding cache 有权
公开(公告)号：US09612963B2
公开(公告)日：2017-04-04
申请号：US15241206
申请日：2016-08-19
申请人： International Business Machines Corporation
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell
IPC分类号： G06F12/08 , G06F12/0862 , G06F12/0866 , G06F12/0842
CPC分类号： G06F12/0877 , G06F9/30043 , G06F9/3826 , G06F9/3834 , G06F12/0806 , G06F12/0833 , G06F12/0842 , G06F12/0862 , G06F12/0864 , G06F12/0866 , G06F12/0868 , G06F12/0875 , G06F12/0895 , G06F12/12 , G06F12/128 , G06F2212/1021 , G06F2212/1024 , G06F2212/214 , G06F2212/452 , G06F2212/60 , G06F2212/6026 , G06F2212/608 , G06F2212/62 , G06F2212/621
摘要： A load request is received to retrieve a piece of data from a location in memory and the load request follows one or more store requests in a set of instructions to store a piece of data in the location in memory. One or more possible locations in a cache for a piece of data corresponding to the location in memory is determined. Each possible location of the one or more possible locations in the cache is determined. It is then determined if at least one location of the one or more possible locations contains data to be stored in the location in memory. Data in one location of the at least one location is loaded, the data in the one location is from a store request of the one or more store requests and the store request is closest in the set of instructions to the load request.

33. 发明申请

US20170091104A1 APPARATUS AND METHOD FOR PREFETCHING 审中-公开
公开(公告)号：US20170091104A1
公开(公告)日：2017-03-30
申请号：US14870594
申请日：2015-09-30
申请人： ARM LIMITED
发明人： Todd RAFACZ , Huzefa SANJELIWALA
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/1016 , G06F2212/1021 , G06F2212/602 , G06F2212/6024 , G06F2212/6026
摘要： Prefetch apparatus and a method of prefetching are presented. The prefetch apparatus monitors access requests, each having an access request address, and has request tracking storage to store region entries for regions of memory space which each span multiple access request addresses. The request tracking storage keeps access information for access requests received in their corresponding region entries. When a new region access request is received, which belongs to a new region for which there is no region entry, and when the request tracking storage has an adjacent region entry for which the access information shows that at least a predetermined number of the access request addresses have been accessed, a page mode region prefetching process is initiated for all access request addresses in the new region.

34. 发明申请

US20170091093A1 METHOD AND APPARATUS FOR UNNEEDED BLOCK PREDICTION IN A COMPUTING SYSTEM HAVING A LAST LEVEL CACHE AND A MULTI-LEVEL SYSTEM MEMORY 审中-公开
公开(公告)号：US20170091093A1
公开(公告)日：2017-03-30
申请号：US14865617
申请日：2015-09-25
申请人： ZHE WANG , CHRISTOPHER B. WILKERSON , ZESHAN A. CHISHTI , SETH H. PUGSLEY , ALAA R. ALAMELDEEN , SHIH-LIEN L. LU
发明人： ZHE WANG , CHRISTOPHER B. WILKERSON , ZESHAN A. CHISHTI , SETH H. PUGSLEY , ALAA R. ALAMELDEEN , SHIH-LIEN L. LU
IPC分类号： G06F12/08 , G06F3/06
CPC分类号： G06F12/0811 , G06F3/0619 , G06F3/065 , G06F3/0685 , G06F12/0862 , G06F12/0888 , G06F12/0893 , G06F2212/283 , G06F2212/6026 , G06F2212/7202
摘要： An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.

35. 发明申请

US20170060755A1 METHOD FOR LOAD INSTRUCTION SPECULATION PAST OLDER STORE INSTRUCTIONS 审中-公开
标题翻译：用于负载指令分析的方法过去旧的存储指令
公开(公告)号：US20170060755A1
公开(公告)日：2017-03-02
申请号：US14838561
申请日：2015-08-28
申请人： Oracle International Corporation
发明人： Yuan Chou
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0875 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F12/0811 , G06F12/0862 , G06F12/128 , G06F2212/283 , G06F2212/452 , G06F2212/6026
摘要： A system includes a memory, a cache including multiple cache lines; and a processor. The processor may be configured to retrieve, from a first cache line, a first instruction to store data in a memory location at an address in the memory. The processor may be configured to retrieve, from a second cache line, a second instruction to read the memory location at the address in the memory. The second instruction may be retrieved after the first instruction. The processor may be configured to execute the second instruction at a first time dependent upon a value of a first entry in a table, wherein the first entry is selected dependent upon a value in the second cache line. The processor may be configured to execute the first instruction at a second time, after the first time, and invalidate the second instruction at a third time, after the second time.
摘要翻译：系统包括存储器，包括多个高速缓存行的高速缓存; 和处理器。处理器可以被配置为从第一高速缓存行检索第一指令以将数据存储在存储器中的地址处的存储器位置。处理器可以被配置为从第二高速缓存行检索第二指令以读取存储器中地址处的存储器位置。可以在第一指令之后检索第二指令。处理器可以被配置为在第一时间执行取决于表中的第一条目的值的第二指令，其中根据第二高速缓存行中的值选择第一条目。处理器可以被配置为在第一次之后的第二时间执行第一指令，并且在第二时间之后在第三时间使第二指令无效。

36. 发明授权

US09575897B2 Processor with efficient processing of recurring load instructions from nearby memory addresses 有权
标题翻译：处理器可以从附近的存储器地址处理循环加载指令
公开(公告)号：US09575897B2
公开(公告)日：2017-02-21
申请号：US14794837
申请日：2015-07-09
申请人： Centipede Semi Ltd.
发明人： Noam Mizrahi , Jonathan Friedmann
IPC分类号： G06F12/08 , G06F9/30 , G06F9/38 , G06F9/45
CPC分类号： G06F12/0875 , G06F8/4442 , G06F9/30181 , G06F9/30196 , G06F9/345 , G06F9/35 , G06F9/383 , G06F9/3832 , G06F9/3834 , G06F9/384 , G06F9/3851 , G06F9/3867 , G06F12/0862 , G06F2212/452 , G06F2212/6026
摘要： A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. Based on respective formats of the memory addresses specified in the symbolic expressions, a sequence of load instructions that access a predictable pattern of memory addresses in the external memory is identified. At least one cache line that includes a plurality of data values is retrieved from the external memory. Based on the predictable pattern, two or more of the data values that are requested by respective load instructions in the sequence are saved from the cache line to the internal memory. The saved data values are assigned to be served from the internal memory to one or more instructions that depend on the respective load instructions.
摘要翻译：一种方法在处理器中包括包括存储器访问指令的处理程序代码，其中至少一些存储器访问指令包括根据一个或多个寄存器名称指定外部存储器中的存储器地址的符号表达式。基于在符号表达式中指定的存储器地址的相应格式，识别访问外部存储器中的可预测的存储器地址模式的加载指令序列。从外部存储器检索包括多个数据值的至少一个高速缓存行。基于可预测的模式，将序列中的各个加载指令请求的两个或多个数据值从高速缓存行保存到内部存储器。保存的数据值被分配为从内部存储器提供到依赖于相应负载指令的一个或多个指令。

37. 发明授权

US09529721B2 Control device, and storage system 有权
标题翻译：控制装置和存储系统
公开(公告)号：US09529721B2
公开(公告)日：2016-12-27
申请号：US14196290
申请日：2014-03-04
申请人： FUJITSU LIMITED
发明人： Takeshi Watanabe , Kazuhiko Ikeuchi , Chikashi Maeda , Kazuhiro Urata , Yukari Tsuchiyama , Norihide Kubota , Kenji Kobayashi , Ryota Tsukahara
IPC分类号： G06F3/00 , G06F13/00 , G06F13/28 , G06F12/08 , G06F3/06
CPC分类号： G06F12/0862 , G06F3/0611 , G06F3/0659 , G06F3/0689 , G06F2212/6026
摘要： A control device that controls a reading process of information stored in a unit storage area under control of the control device and a unit storage area under control of a different control device in a distributed manner, the control device includes a processor. The processor executes a procedure including determining whether or not the reading process is a sequential reading process that reads information stored in a unit storage area under control of the control device in an order of logical addresses and whether or not a reading target area of the sequential reading process includes a last address in the unit storage area, and reporting to the different control device control information related to a sequential reading process including the last address determined by the first determination unit.
摘要翻译：一种控制装置，其控制在所述控制装置的控制下存储在单元存储区域中的信息的读取处理和在不同的控制装置的分布式控制下的单元存储区域，所述控制装置包括处理器。处理器执行一个过程，包括确定读取过程是否是按照逻辑地址的顺序读取在控制设备的控制下存储在单元存储区域中的信息的顺序读取处理，以及是否顺序地读取目标区域读取处理包括单元存储区域中的最后地址，并且向不同的控制装置报告与包括由第一确定单元确定的最后地址的顺序读取处理相关的控制信息。

38. 发明申请

US20160357677A1 MULTIPLE DATA PREFETCHERS THAT DEFER TO ONE ANOTHER BASED ON PREFETCH EFFECTIVENESS BY MEMORY ACCESS TYPE 有权
标题翻译：基于存储访问类型的预先有效性的多个数据前缀
公开(公告)号：US20160357677A1
公开(公告)日：2016-12-08
申请号：US14891331
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： RODNEY E. HOOKER , DOUGLAS R. REED , JOHN MICHAEL GREER , COLIN EDDY
IPC分类号： G06F12/0862
CPC分类号： G06F12/0862 , G06F8/4442 , G06F9/30047 , G06F9/3455 , G06F9/3802 , G06F9/383 , G06F12/0811 , G06F12/0848 , G06F12/127 , G06F2212/1016 , G06F2212/1044 , G06F2212/502 , G06F2212/6026
摘要： A processor includes a first prefetcher that prefetches data in response to memory accesses and a second prefetcher that prefetches data in response to memory accesses. Each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table that holds first scores that indicate effectiveness of the first prefetcher to prefetch data with respect to the plurality of predetermined MATs and second scores that indicate effectiveness of the second prefetcher to prefetch data with respect to the plurality of predetermined MATs. The first and second prefetchers selectively defer to one another with respect to data prefetches based on their relative scores in the table and the associated MATs of the memory accesses.
摘要翻译：处理器包括：第一预取器，其响应于存储器访问预取数据;以及第二预取器，其响应于存储器访问预取数据。每个存储器访问具有多个预定MAT的相关联的存储器访问类型（MAT）。处理器还包括一个表，其保存表示第一预取器相对于多个预定MAT预取数据的有效性的第一分数，以及指示第二预取器相对于多个预定MAT预取数据的有效性的第二分数。第一和第二预取器基于其在表中的相对分数和存储器访问的相关联的MAT相对于数据预取来选择性地彼此延迟。

39. 发明授权

US09507596B2 Instruction and logic for prefetcher throttling based on counts of memory accesses to data sources 有权
标题翻译：基于对数据源的内存访问计数的预取器调节的指令和逻辑
公开(公告)号：US09507596B2
公开(公告)日：2016-11-29
申请号：US14471261
申请日：2014-08-28
申请人： Intel Corporation
发明人： Ashok Jagannathan , Prabhat Jain , Krishna N. Vinod , Avinash Sodani
IPC分类号： G06F13/00 , G06F9/30 , G06F12/08 , G06F9/38 , G06F12/06
CPC分类号： G06F9/30047 , G06F9/383 , G06F9/3887 , G06F12/0646 , G06F12/0862 , G06F2212/6026 , G06F2212/6028
摘要： A processor includes a core, a prefetcher, and a prefetcher control module. The prefetcher includes logic to make speculative prefetch requests through a memory subsystem for an element for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to determine counts of memory accesses to two types of memory and, based upon the counts and the type of memory, reduce the speculative prefetch requests of the prefetcher.
摘要翻译：处理器包括核心，预取器和预取器控制模块。预取器包括通过内存子系统进行推测预取请求的逻辑，用于由核心执行的元素，以及将预取元素存储在高速缓存中的逻辑。预取器控制模块包括用于确定对两种类型的存储器的存储器访问的计数的逻辑，并且基于计数和存储器的类型，减少预取器的推测性预取请求。

40. 发明授权

US09483406B2 Communicating prefetchers that throttle one another 有权
标题翻译：沟通相互压制的预取器
公开(公告)号：US09483406B2
公开(公告)日：2016-11-01
申请号：US14315064
申请日：2014-06-25
申请人： VIA TECHNOLOGIES, INC.
发明人： Rodney E. Hooker , John Michael Greer
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862 , G06F9/383 , G06F2212/502 , G06F2212/6026
摘要： A microprocessor includes a first hardware data prefetcher that prefetches data into the microprocessor according to a first algorithm. The microprocessor also includes a second hardware data prefetcher that prefetches data into the microprocessor according to a second algorithm, wherein the first and second algorithms are different. The second prefetcher detects that it is prefetching data into the microprocessor according to the second algorithm in excess of a first predetermined rate and, in response, sends a throttle indication to the first prefetcher. The first prefetcher prefetches data into the microprocessor according to the first algorithm at below a second predetermined rate in response to receiving the throttle indication from the second prefetcher.
摘要翻译：微处理器包括根据第一算法将数据预取到微处理器的第一硬件数据预取器。微处理器还包括第二硬件数据预取器，其根据第二算法将数据预取到微处理器中，其中第一和第二算法是不同的。第二预取器检测到根据第二算法将数据预取到微处理器中超过第一预定速率，并且作为响应，向第一预取器发送节气门指示。响应于从第二预取器接收到节气门指示，第一预取器根据第一算法在低于第二预定速率的情况下将数据预取到微处理器中。

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