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1. 发明申请

US20190065376A1 UTILIZATION-BASED THROTTLING OF HARDWARE PREFETCHERS 审中-公开
公开(公告)号：US20190065376A1
公开(公告)日：2019-02-28
申请号：US15691302
申请日：2017-08-30
申请人： Oracle International Corporation
发明人： Hyunjin Abraham Lee , Yuan Chou , John Pape
IPC分类号： G06F12/0862 , G06F12/0855
摘要： An system for prefetching data for a processor includes a processor core, a memory, a cache memory, and a prefetch circuit. The memory may be configured to store information for use by the processor core. The cache memory may be configured to issue a fetch request for information from the memory for use by the processor core. The prefetch circuit may be configured to issue a prefetch request for information from the memory to store in the cache memory using a predicted address, and to monitor, over a particular time interval, an amount of fetch requests from the cache memory and prefetch requests from the prefetch circuit. The prefetch circuit may also be configured to disable prefetch requests from the memory for a subsequent time interval in response to a determination that the amount satisfies a threshold amount.

2. 发明授权

US11099849B2 Method for reducing fetch cycles for return-type instructions 有权
公开(公告)号：US11099849B2
公开(公告)日：2021-08-24
申请号：US15254648
申请日：2016-09-01
申请人： Oracle International Corporation
发明人： Yuan Chou , Manish Shah , Richa Aggarwal
IPC分类号： G06F9/38
摘要： An apparatus includes a branch target cache configured to store one or more branch addresses, a memory configured to store a return target stack, and a circuit. The circuit may be configured to determine, for a group of one or more fetched instructions, a prediction value indicative of whether the group includes a return instruction. In response to the prediction value indicating that the group includes a return instruction, the circuit may be further configured to select a return address from the return target stack. The circuit may also be configured to determine a hit or miss indication in the branch target cache for the group, and to, in response to receiving a miss indication from the branch target cache, select the return address as a target address for the return instruction.

3. 发明申请

US20180121200A1 HYBRID LOOKAHEAD BRANCH TARGET CACHE 审中-公开
公开(公告)号：US20180121200A1
公开(公告)日：2018-05-03
申请号：US15340106
申请日：2016-11-01
申请人： Oracle International Corporation
发明人： Yuan Chou , Manish Shah
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
摘要： An apparatus is disclosed, the apparatus including a branch target cache memory configured to store one or more entries. Each entry of the one or more entries may include an address tag and a corresponding target address. The apparatus may also include a control circuit configured to check for at least one taken branch instruction in a group of one or more instructions fetched using a current address. The control circuit may be further configured to generate an address tag corresponding to the group of one or more instructions using another address used prior to the current address in response to a determination that the group of one or more instructions includes a taken branch instruction. In addition, the control circuit may be configured to store the corresponding address tag and a target address associated with the taken branch instruction in a particular entry in the branch target cache memory.

4. 发明申请

US20150356014A1 DYNAMICALLY ADJUSTING THE HARDWARE STREAM PREFETCHER PREFETCH AHEAD DISTANCE 有权
标题翻译：硬件流程前缀调整前景距离动态调整
公开(公告)号：US20150356014A1
公开(公告)日：2015-12-10
申请号：US14295831
申请日：2014-06-04
申请人： Oracle International Corporation
发明人： Vijay Sathish , Yuan Chou
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： An apparatus for prefetching data for a processor is presented. The apparatus may include a memory, a first counter, a second counter, and a control circuit. The memory may include a table with at least one entry in which the at least one entry may include an expected address of a next memory access and a next address from which to fetch data, wherein the next address is an offset value different from the expected address. The at least one entry may also include a maximum limit for the offset value. The first counter may increment responsive to an address of a memory access matching the expected address. The second counter may increment responsive to the address of the memory access resulting in a cache miss. The control circuitry may be configured to increment the maximum value of the offset value dependent upon a value of the second counter.
摘要翻译：提出了一种用于为处理器预取数据的设备。该装置可以包括存储器，第一计数器，第二计数器和控制电路。存储器可以包括具有至少一个条目的表，其中至少一个条目可以包括下一个存储器访问的预期地址和从其获取数据的下一个地址，其中下一个地址是与预期的不同的偏移值地址。该至少一个条目还可以包括偏移值的最大限制。第一个计数器可以响应于匹配预期地址的存储器访问的地址来增加。第二计数器可以响应于存储器访问的地址而增加，导致高速缓存未命中。控制电路可以被配置为根据第二计数器的值增加偏移值的最大值。

5. 发明授权

US10747540B2 Hybrid lookahead branch target cache 有权
公开(公告)号：US10747540B2
公开(公告)日：2020-08-18
申请号：US15340106
申请日：2016-11-01
申请人： Oracle International Corporation
发明人： Yuan Chou , Manish Shah
IPC分类号： G06F9/38
摘要： An apparatus is disclosed, the apparatus including a branch target cache memory configured to store one or more entries. Each entry of the one or more entries may include an address tag and a corresponding target address. The apparatus may also include a control circuit configured to check for at least one taken branch instruction in a group of one or more instructions fetched using a current address. The control circuit may be further configured to generate an address tag corresponding to the group of one or more instructions using another address used prior to the current address in response to a determination that the group of one or more instructions includes a taken branch instruction. In addition, the control circuit may be configured to store the corresponding address tag and a target address associated with the taken branch instruction in a particular entry in the branch target cache memory.

6. 发明授权

US10073789B2 Method for load instruction speculation past older store instructions 有权
公开(公告)号：US10073789B2
公开(公告)日：2018-09-11
申请号：US14838561
申请日：2015-08-28
申请人： Oracle International Corporation
发明人： Yuan Chou
IPC分类号： G06F12/08 , G06F12/12 , G06F12/0875 , G06F12/0811 , G06F12/128 , G06F12/0862
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F12/0859 , G06F2212/1021 , G06F2212/507
摘要： A system includes a memory, a cache including multiple cache lines; and a processor. The processor may be configured to retrieve, from a first cache line, a first instruction to store data in a memory location at an address in the memory. The processor may be configured to retrieve, from a second cache line, a second instruction to read the memory location at the address in the memory. The second instruction may be retrieved after the first instruction. The processor may be configured to execute the second instruction at a first time dependent upon a value of a first entry in a table, wherein the first entry is selected dependent upon a value in the second cache line. The processor may be configured to execute the first instruction at a second time, after the first time, and invalidate the second instruction at a third time, after the second time.

7. 发明授权

US09785574B2 Translation lookaside buffer that employs spacial locality 有权
公开(公告)号：US09785574B2
公开(公告)日：2017-10-10
申请号：US14794438
申请日：2015-07-08
申请人： Oracle International Corporation
发明人： Yuan Chou
IPC分类号： G06F12/00 , G06F12/1027
CPC分类号： G06F12/1027 , G06F2212/654 , G06F2212/68
摘要： A system may include a memory that includes a plurality of pages, a processor, and a translation lookaside buffer (TLB) that includes a plurality of entries. The processor may be configured to access data from a subset of the plurality of pages dependent upon a first virtual address. The TLB may be configured to compare the first virtual address to respective address information included in each entry of the plurality of entries. The TLB may be further configured to add a new entry to the plurality of entries in response to a determination that the first virtual address fails to match the respective address information included in each entry of the plurality of entries. The new entry may include address information corresponding to at least two pages of the subset of the plurality pages.

8. 发明授权

US10430342B2 Optimizing thread selection at fetch, select, and commit stages of processor core pipeline 有权
公开(公告)号：US10430342B2
公开(公告)日：2019-10-01
申请号：US14945054
申请日：2015-11-18
申请人： Oracle International Corporation
发明人： Yuan Chou , Gideon Levinsky , Manish Shah , Robert Golla , Matthew Smittle
IPC分类号： G06F12/0875 , G06F9/38
摘要： An apparatus includes a buffer configured to store a plurality of instructions previously fetched from a memory, wherein each instruction of the plurality of instructions may be included in a respective thread of a plurality of threads. The apparatus also includes control circuitry configured to select a given thread of the plurality of threads dependent upon a number of instructions in the buffer that are included in the given thread. The control circuitry is also configured to fetch a respective instruction corresponding to the given thread from the memory, and to store the respective instruction in the buffer.

9. 发明申请

US20190065377A1 MULTI-LINE DATA PREFETCHING USING DYNAMIC PREFETCH DEPTH 审中-公开
公开(公告)号：US20190065377A1
公开(公告)日：2019-02-28
申请号：US15691351
申请日：2017-08-30
申请人： Oracle International Corporation
发明人： Hyunjin Abraham Lee , Yuan Chou , John Pape
IPC分类号： G06F12/0862 , G06F12/0855
摘要： A system for prefetching data for a processor includes a processor core, a memory configured to store information for use by the processor core, a cache memory configured to fetch and store information from the memory, and a prefetch circuit. The prefetch circuit may be configured to issue a multi-group prefetch request to retrieve information from the memory to store in the cache memory using a predicted address. The multi-group prefetch request may include a depth value indicative of a number of fetch groups to retrieve. The prefetch circuit may also be configured to generate an accuracy value based on a cache hit rate of prefetched information over a particular time interval, and to modify the depth value based on the accuracy value.

10. 发明申请

US20170139706A1 OPTIMIZING THREAD SELECTION AT FETCH, SELECT, AND COMMIT STAGES OF PROCESSOR CORE PIPELINE 审中-公开
公开(公告)号：US20170139706A1
公开(公告)日：2017-05-18
申请号：US14945054
申请日：2015-11-18
申请人： Oracle International Corporation
发明人： Yuan Chou , Gideon Levinsky , Manish Shah , Robert Golla , Matthew Smittle
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F12/0875 , G06F9/30087 , G06F9/3009 , G06F9/30189 , G06F9/3851 , G06F2212/452
摘要： An apparatus includes a buffer configured to store a plurality of instructions previously fetched from a memory, wherein each instruction of the plurality of instructions may be included in a respective thread of a plurality of threads. The apparatus also includes control circuitry configured to select a given thread of the plurality of threads dependent upon a number of instructions in the buffer that are included in the given thread. The control circuitry is also configured to fetch a respective instruction corresponding to the given thread from the memory, and to store the respective instruction in the buffer.

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