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31. 发明授权

US07698079B2 Characterizing across-die process variation 失效
标题翻译：表征跨模工艺变化
公开(公告)号：US07698079B2
公开(公告)日：2010-04-13
申请号：US11946571
申请日：2007-11-28
申请人： Dhruva J. Acharyya , Kanak B. Agarwal
发明人： Dhruva J. Acharyya , Kanak B. Agarwal
IPC分类号： G01R19/00
CPC分类号： G01R31/31718 , G01R31/3008
摘要： Measurement of individual quiescent supply currents from multiple power supply pads located across a semiconductor die provides a means of characterizing across-die variation. A ratio is created by combining the individual pad supply current with the sum of all pad supply currents for a given die. An n-tuple is formed from the set of ratios for all pad supply currents to provide a unique signature for different across-die variation profiles.
摘要翻译：跨越半导体管芯的多个电源焊盘测量单个静态电源提供了一种表征跨裸片变化的方法。通过将各个焊盘供应电流与给定裸片的所有焊盘电源电流的总和组合来产生比率。由所有焊盘电源电流的一组比率形成一个n元组，以为不同的跨模变化曲线提供唯一的标记。

32. 发明申请

US20100070211A1 ROLLING AVERAGE TEST 审中-公开
标题翻译：滚动平均测试
公开(公告)号：US20100070211A1
公开(公告)日：2010-03-18
申请号：US12210090
申请日：2008-09-12
申请人： Brian Surette , Thomas W. Kelly , James E. Martin , Bernard Tan
发明人： Brian Surette , Thomas W. Kelly , James E. Martin , Bernard Tan
IPC分类号： G01R31/26
CPC分类号： G01R31/2894 , G01R31/3167 , G01R31/31718
摘要： A system and method for performing dynamic in-line testing of semiconductor devices sequentially tests a plurality of semiconductor devices. Test data associated with a predetermined number of semiconductor devices of the sequentially tested semiconductor devices is stored in a data structure. After test data corresponding to a predetermined number of semiconductor devices is stored in the data structure, the following steps are iteratively performed. Statistics concerning the selected devices are calculated using the associated test data. A device that fails to meet a precision setting based on the statistics is marked as an outlier device. Test data stored in the data structure corresponding to an earliest tested semiconductor device in sequence is evicted from the data structure. Test data associated with the next passing tested semiconductor device in sequence is stored in the data structure.
摘要翻译：用于执行半导体器件的动态在线测试的系统和方法顺序地测试多个半导体器件。与依次测试的半导体器件的预定数量的半导体器件相关联的测试数据被存储在数据结构中。对应于预定数量的半导体器件的测试数据被存储在数据结构中之后，迭代地执行以下步骤。使用关联的测试数据计算所选设备的统计数据。基于统计信息不符合精度设置的设备被标记为异常值设备。与数据结构对应的数据结构中存储的测试数据依次从数据结构中消失。与下一次通过的测试半导体器件相关的测试数据按顺序存储在数据结构中。

33. 发明授权

US07587292B2 Method of monitoring a semiconductor manufacturing trend 有权
标题翻译：监控半导体制造趋势的方法
公开(公告)号：US07587292B2
公开(公告)日：2009-09-08
申请号：US11344664
申请日：2006-02-01
申请人： Dieter Rathei
发明人： Dieter Rathei
IPC分类号： G06F19/00 , G06F17/40
CPC分类号： G01R31/2894 , G01R31/31718 , G01R31/318314
摘要： A parametric parameter is selected, which has an upper specification limit and a lower specification limit. A storage percentile is determined. The storage percentile is equal to a product yield percentage if the number of the set of measurements greater than the upper specification limit exceeds the number of the set of measurements lower than the lower specification limit, and is equal to the product yield percentage subtracted from one hundred percent if the number of the set of measurements less than the lower specification limit exceeds the number of the set of measurements greater than the upper specification limit. A measurement closest to the storage percentile is stored.
摘要翻译：选择参数参数，其具有较高的规格限制和较低的规格限制。确定存储百分位数。如果大于上限规格限值的测量值的数量超过比较低规格限值低的测量值的数量，则存储百分位数等于产品产量百分比，并且等于从一个百分之百，如果小于较低规格限值的测量值的数量超过大于上限规格的测量值的数量。存储最接近存储百分位数的测量。

34. 发明授权

US07577541B1 Test services provider 失效
标题翻译：测试服务提供商
公开(公告)号：US07577541B1
公开(公告)日：2009-08-18
申请号：US11313323
申请日：2005-12-21
申请人： Orville Jay Potter, IV , Peter Gerber , Michael Paul Robinson
发明人： Orville Jay Potter, IV , Peter Gerber , Michael Paul Robinson
IPC分类号： G01M19/00
CPC分类号： G01R31/31718 , G01R31/2834
摘要： A test services provider is an object that is arranged to provide a standardized interface for calling test harness provided functionality. The test services provider is not tied to a specific test harness, and provides a standard interface such that both test harness functionality and test cases can be written without beforehand knowledge of the other. In operation, the test harness registers the test services that provides with the test service provider, and the test cases retrieve the registered test services from the test harness as needed. Accordingly, the test case does not have to query the test harness itself for the object that provides the desired test harness functionality, but rather uses a standardized interface provided by the test services provider to retrieve the desired test services.
摘要翻译：测试服务提供商是被安排为提供调用测试线束提供的功能的标准化接口的对象。测试服务提供商不与特定的测试工具绑定，并且提供了一个标准接口，以便可以在不事先知道另一个测试用例的情况下编写测试工具功能和测试用例。在运行中，测试线束注册与测试服务提供商提供的测试服务，测试用例根据需要从测试工具中检索注册的测试服务。因此，测试用例不必向测试工具本身查询提供所需测试功能的对象，而是使用由测试服务提供商提供的标准化接口来检索所需的测试服务。

35. 发明授权

US07569402B2 Chip data providing system and chip data providing server used therefore 有权
标题翻译：因此使用芯片数据提供系统和芯片数据提供服务器
公开(公告)号：US07569402B2
公开(公告)日：2009-08-04
申请号：US10969323
申请日：2004-10-20
申请人： Kunihiro Kawahara , Kazuya Saito
发明人： Kunihiro Kawahara , Kazuya Saito
IPC分类号： H01L21/00 , G06F19/00
CPC分类号： G01R31/31718 , G01R31/31707 , G06Q50/04 , Y02P90/30
摘要： A chip data providing system is provided. The chip data providing system is equipped with an inspection device for inspecting each chip after processing steps of forming integrated circuits on a plurality chips included in a semiconductor wafer are completed, an inspection server that generates, based on an inspection result, first chip data including information concerning the inspection result of each of the chips, and a chip data providing server that generates, based on the first chip data generated by the inspection server and information concerning an assembly enterprise stored in advance, second chip data in a format suitable for a system of the assembly enterprise that selects and uses the plurality of chips included in the semiconductor wafer, and provides the second chip data to the assembly enterprise.
摘要翻译：提供了一种芯片数据提供系统。芯片数据提供系统配备有检查装置，用于在完成包括在半导体晶片中的多个芯片上形成集成电路的处理步骤之后检查每个芯片;检查服务器，其基于检查结果生成包括关于每个芯片的检查结果的信息，以及芯片数据提供服务器，其基于由检查服务器生成的第一芯片数据和关于预先存储的组装企业的信息，生成适合于组装企业的系统，其选择并使用包括在半导体晶片中的多个芯片，并且向组装企业提供第二芯片数据。

36. 发明授权

US07555358B2 Process and method for continuous, non lot-based integrated circuit manufacturing 有权
标题翻译：连续，非批量集成电路制造的工艺和方法
公开(公告)号：US07555358B2
公开(公告)日：2009-06-30
申请号：US10205918
申请日：2002-07-25
申请人： Mark L. Jones , Gregory A. Barnett
发明人： Mark L. Jones , Gregory A. Barnett
IPC分类号： G06F19/00
CPC分类号： G05B19/128 , G01R31/31718 , G05B2219/31296 , G05B2219/45026 , G06F11/006 , H01L27/0207 , H01L2223/5444 , Y02P90/10
摘要： A method for continuous, non lot-based manufacturing of integrated circuit (IC) devices of the type to each have a unique fuse identification (ID) includes: reading the fuse ID of each of the IC devices; advancing multiple lots of the IC devices through, for example, a test step in the manufacturing process in a substantially continuous manner; generating data, such as test data, related to the advancement of each of the IC devices through the step in the process; and associating the data generated for each of the IC devices with the fuse ID of its associated IC device.
摘要翻译：一种用于连续，非批量制造这种类型的集成电路（IC）装置的方法，每种具有唯一的熔丝识别（ID）包括：读取每个IC器件的熔丝ID; 通过例如基本上连续的制造过程中的测试步骤来推进多批IC器件; 通过该过程中的步骤生成与每个IC设备的进步相关的数据，例如测试数据; 并且将针对每个IC设备生成的数据与其相关联的IC设备的熔丝ID相关联。

37. 发明授权

US07514914B2 Test circuits of an apparatus for testing system-in-package devices 失效
标题翻译：用于测试系统级封装器件的设备的测试电路
公开(公告)号：US07514914B2
公开(公告)日：2009-04-07
申请号：US11786760
申请日：2007-04-12
申请人： James E. Hopkins , Michael Peter Costello , Herbert Tsai , Ching-Too Chen
发明人： James E. Hopkins , Michael Peter Costello , Herbert Tsai , Ching-Too Chen
IPC分类号： G01R31/02
CPC分类号： G01R31/2893 , G01R31/31718 , G01R31/31905
摘要： Apparatus for testing System-In-Package (SIP) devices each having a plurality of electrical leads is described. The apparatus utilizes industry standard JEDEC trays and tests all devices in such trays at the same time. The apparatus of the illustrative embodiment comprises a test hive comprising: a plurality of test circuits corresponding in number to the number of cells in the tray; and a plurality of groups of test contacts, each of the groups of the test contacts being coupled to one of the test circuits and being oriented to engage the plurality of electrical contacts of SIP device disposed in a corresponding one of the cells, the test hive being operable to simultaneously, electrically test all of the SIP devices in each tray engaged by the hive without removing the SIP devices from the tray.
摘要翻译：描述了具有多个电引线的用于测试系统级封装（SIP）器件的装置。该设备采用行业标准的JEDEC托盘，同时对这些托盘中的所有设备进行测试。说明性实施例的装置包括测试蜂巢，其包括：多个对应于托盘中的小区数目的测试电路; 以及多组测试触点，所述测试触点组中的每一个耦合到所述测试电路中的一个并且被定向成接合设置在相应的一个单元中的SIP设备的多个电触头，所述测试配置单元可操作以同时电测试由蜂巢接合的每个托盘中的所有SIP设备，而不从托盘移除SIP设备。

38. 发明申请

US20090089005A1 GENERATION OF TEST SPECIFICATIONS BASED ON MEASURED DATA POINTS 审中-公开
标题翻译：基于测量数据点的测试规范的生成
公开(公告)号：US20090089005A1
公开(公告)日：2009-04-02
申请号：US11863924
申请日：2007-09-28
申请人： Geoff Hopcraft , Joseph M. Gorin
发明人： Geoff Hopcraft , Joseph M. Gorin
IPC分类号： G06F19/00
CPC分类号： G01R31/31718 , G01R31/31908
摘要： Autonomous or machine generation of test specifications can be achieved by capturing the measured test data of a device and then using the captured test data to build a test specification, such as a limit line, for subsequent testing of similar devices. The generated test specification is typically adapted for use with respect to limited resources, such as through use of a piece-wise linear configuration. In an embodiment, the number of piece-wise linear portions of the generated test specification is minimized or otherwise optimized. In embodiments, the generated test specification is adjusted to accommodate expected measurement variation, such as thermal noise, device process variation, random jitter, etc., and, if desired, adjusted to allow for changes in test accuracy of subsequent tests. In one embodiment, one or more test measurement inaccuracies are eliminated in the construction of the limit line.
摘要翻译：测试规范的自主或机器生成可以通过捕获测量的设备测试数据，然后使用捕获的测试数据来构建测试规范（如限制线），以便后续测试类似设备来实现。生成的测试规范通常适用于有限的资源使用，例如通过使用分段线性配置。在一个实施例中，生成的测试规范的分段线性部分的数量被最小化或以其他方式优化。在实施例中，生成的测试规范被调整以适应预期的测量变化，例如热噪声，设备过程变化，随机抖动等，并且如果需要，被调整以允许后续测试的测试精度的变化。在一个实施例中，在限制线的构造中消除了一个或多个测试测量不准确性。

39. 发明授权

US07502659B2 Sorting a group of integrated circuit devices for those devices requiring special testing 失效
标题翻译：对需要特殊测试的那些设备对一组集成电路设备进行排序
公开(公告)号：US07502659B2
公开(公告)日：2009-03-10
申请号：US11543246
申请日：2006-10-03
申请人： Raymond J. Beffa
发明人： Raymond J. Beffa
IPC分类号： G06F19/00
CPC分类号： G01R31/2894 , G01R31/31718 , G01R31/319 , G06F11/006 , H01L21/67271 , H01L22/14 , H01L22/20 , H01L2223/5444
摘要： A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing includes storing fabrication deviation data, probe data, and test data in association with the fuse ID of each of the devices indicating each of the devices requires either enhanced reliability testing or standard testing. The fuse ID of each of the devices is then automatically read before, during, or after standard testing of the devices. The testing process requirement data stored in association with the fuse ID of each of the devices is then accessed, and the devices are sorted in accordance with the accessed data into those devices requiring enhanced reliability testing and those requiring standard testing.
摘要翻译：将具有熔丝识别（ID）的类型的集成电路（IC）装置分类到需要增强的可靠性测试的那些装置和需要进行标准测试的装置的方法包括存储制造偏差数据，探针数据和与熔丝ID相关联的测试数据指示每个设备的每个设备需要增强的可靠性测试或标准测试。然后在设备的标准测试之前，期间或之后自动读取每个设备的熔丝ID。然后访问与每个设备的熔丝ID相关联地存储的测试过程要求数据，并且根据所访问的数据将设备分类到需要增强的可靠性测试的设备和需要标准测试的那些设备中。

40. 发明授权

US07492179B2 Systems and methods for reducing testing times on integrated circuit dies 有权
标题翻译：减少集成电路裸片测试时间的系统和方法
公开(公告)号：US07492179B2
公开(公告)日：2009-02-17
申请号：US11279240
申请日：2006-04-10
申请人： Chien-Jung Chiu , Hsing-Ya Huo , Tsung-Yu Lee
发明人： Chien-Jung Chiu , Hsing-Ya Huo , Tsung-Yu Lee
IPC分类号： G01R31/26
CPC分类号： G01R31/31718 , G11C29/006 , G11C2029/0403
摘要： Disclosed herein are various embodiments of systems and method for testing dies on semiconductor wafers that reduce testing times on future wafers. The disclosed systems and methods may be employed to determine which BINs, if any, should be reprobed during a second testing pass. Specifically, the disclosed principles provide this determination based on the relationship between the yield recovery rate of a single BIN in view of the recovery rate for all BINs on the wafer, and the reprobe rate of that single BIN in view of the reprobe rate for all of the BINs. With this approach, both the recovery rate and the reprobe rate for a single BIN are evaluated as a percentage of the recovery rate or reprobe rate for all of the BINs on the wafer.
摘要翻译：本文公开了用于在半导体晶片上测试管芯的系统和方法的各种实施例，其减少对未来晶片的测试时间。所公开的系统和方法可用于确定在第二次测试通过期间应该重新布置哪些BIN（如果有的话）。具体地，所公开的原理基于从晶片上的所有BIN的恢复速率来的单个BIN的产率恢复率与该单个BIN的重新选择率之间的关系来提供该确定，考虑到所有的BIN的重新选择速率的BIN。通过这种方法，对于单个BIN的回收率和重新选择率都被评估为晶片上所有BIN的回收率或重新选择率的百分比。

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