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    • 31. 发明授权
    • Bistable logic circuit
    • 双向逻辑电路
    • US3633049A
    • 1972-01-04
    • US3633049D
    • 1970-08-07
    • SYLVANIA ELECTRIC PROD
    • PATEL SUMAN H
    • H03K3/286H03K23/66
    • H03K23/665H03K3/286
    • Counter circuit including four bistable stages arranged to count upward through a recurring sequence of combinations of operating states of the bistable stages in response to trigger pulses. An output circuit produces an output signal when the bistable stages have counted upward to the highest count before repeating the sequence. A setting circuit in each bistable stage can switch its stage into either the ''''1'''' or ''''0'''' state at any time during a sequence. Setting signals are applied at input terminals of each setting circuit and are gated in to set the bistable stages simultaneously by a strobe circuit.
    • 包括四个双稳态级的计数器电路,其布置成响应于触发脉冲通过双稳态级的操作状态的组合的循环序列向上计数。 当双稳态级在重复序列之前向上计数到最高计数时,输出电路产生输出信号。 每个双稳态阶段的设置电路可以在序列中的任何时间将其阶段切换到“1”或“0”状态。 设置信号被施加在每个设置电路的输入端,并被门控以通过选通电路同时设置双稳态级。
    • 34. 发明授权
    • Method of manufacturing integrated circuit arrays
    • 制造集成电路阵列的方法
    • US3621562A
    • 1971-11-23
    • US3621562D
    • 1970-04-29
    • SYLVANIA ELECTRIC PROD
    • PATEL HASMUKH M
    • H01L27/118B01J17/00H01L1/16
    • H01L27/11801
    • METHOD OF METALLIZING AN INTEGRATED CIRCUIT NETWORK CONTAINING AN ARRAY OF IDENTICAL CELLS TO PRODUCE A SPECIFIC SYBSYTEM. EACH IDENTICAL CELL INCLUDES SEVERAL GROUPS OF COMPONENTS, EACH GROUP BEING CAPABLE OF BEING INTERCONNECTED IN SEVERAL DIFFERENT ARRANGEMENTS TO FORM SEVERAL DIFFERENT BASIC LOGIC CIRCUITS. A FIRST IDENTICAL METALLIZATION PATTERN IS PLACED ON EACH CELL OF THE ARRAY AND INCLUDES ALL THE DIFFERENT ARRANGEMENTS OF INTERCONNECTIONS BETWEEN THE COMPONENTS OF EACH GROUP OF THE CELL, AND ALSO A BLOCK OF METAL ADJACENT THE CELL. TO COMMIT EACH CELL TO A SPECIFIC LOGIC ARRANGEMENT, METAL IS REMOVED SO THAT EACH GROUP BECOMES ONE SPECIFIC BASIC LOGIC CIRCUIT AND SO THAT THE BLOCK OF METAL BECOMES A FIRST SET OF DISCRETE CONDUCTIVE PATHS. A LAYER OF NON-CONDUCTIVE MATERIAL IS APPLIED OVER THE ARRAY, OPENINGS ARE MADE THEREIN TO EXPOSE APPROPRIATE AREAS OF THE FIRST METALLIAZATION, AND THEN A SECOND METALLIZATION PATTERN IS APPLIED TO FORM A SECOND SET OF CONDUCTIVE PATHS GENERALLY TRANSVERSE TO THE FIRST SET. THE SECOND SET IN CONJUNCTION WITH THE FIRST SET INTERCONNECTS THE BASIC LOGIC CIRCUITS INTO A SPECIFIC SYBSYSTEM.