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1. 发明授权

US3621562A Method of manufacturing integrated circuit arrays 失效
标题翻译：制造集成电路阵列的方法
公开(公告)号：US3621562A
公开(公告)日：1971-11-23
申请号：US3621562D
申请日：1970-04-29
申请人： SYLVANIA ELECTRIC PROD
发明人： PATEL HASMUKH M
IPC分类号： H01L27/118 , B01J17/00 , H01L1/16
CPC分类号： H01L27/11801
摘要： METHOD OF METALLIZING AN INTEGRATED CIRCUIT NETWORK CONTAINING AN ARRAY OF IDENTICAL CELLS TO PRODUCE A SPECIFIC SYBSYTEM. EACH IDENTICAL CELL INCLUDES SEVERAL GROUPS OF COMPONENTS, EACH GROUP BEING CAPABLE OF BEING INTERCONNECTED IN SEVERAL DIFFERENT ARRANGEMENTS TO FORM SEVERAL DIFFERENT BASIC LOGIC CIRCUITS. A FIRST IDENTICAL METALLIZATION PATTERN IS PLACED ON EACH CELL OF THE ARRAY AND INCLUDES ALL THE DIFFERENT ARRANGEMENTS OF INTERCONNECTIONS BETWEEN THE COMPONENTS OF EACH GROUP OF THE CELL, AND ALSO A BLOCK OF METAL ADJACENT THE CELL. TO COMMIT EACH CELL TO A SPECIFIC LOGIC ARRANGEMENT, METAL IS REMOVED SO THAT EACH GROUP BECOMES ONE SPECIFIC BASIC LOGIC CIRCUIT AND SO THAT THE BLOCK OF METAL BECOMES A FIRST SET OF DISCRETE CONDUCTIVE PATHS. A LAYER OF NON-CONDUCTIVE MATERIAL IS APPLIED OVER THE ARRAY, OPENINGS ARE MADE THEREIN TO EXPOSE APPROPRIATE AREAS OF THE FIRST METALLIAZATION, AND THEN A SECOND METALLIZATION PATTERN IS APPLIED TO FORM A SECOND SET OF CONDUCTIVE PATHS GENERALLY TRANSVERSE TO THE FIRST SET. THE SECOND SET IN CONJUNCTION WITH THE FIRST SET INTERCONNECTS THE BASIC LOGIC CIRCUITS INTO A SPECIFIC SYBSYSTEM.

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