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    • 37. 发明授权
    • Shift register circuit
    • 移位寄存器电路
    • US5027382A
    • 1991-06-25
    • US451176
    • 1989-12-15
    • Akihiko HiroeNoriyuki Terao
    • Akihiko HiroeNoriyuki Terao
    • G11C19/00
    • G11C19/00
    • A shift register circuit comprises a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternately connected in series, where a first one of the first clocked gate inverters is adapted to receive an input pulse signal, an output line connected to an output of each of the inverters for outputting an output pulse signal, and a second clocked gate inverter connected to the output of each of the inverters for outputting an output pulse signal. The first clocked gate inverters operate responsive to a first clock signal, and the second clocked gate inverters operate responsive to a second clock signal which is different from the first clock signal.
    • 移位寄存器电路包括串联电路,其包括串联交替连接的多个第一时钟门控反相器和反相器,其中第一时钟门控反相器中的第一个适于接收输入脉冲信号,输出线连接到 输出用于输出输出脉冲信号的每个反相器的输出;以及连接到每个反相器的输出的第二时钟控制反相器,用于输出输出脉冲信号。 第一时钟门反相器响应于第一时钟信号而工作,并且第二时钟门控反相器响应于与第一时钟信号不同的第二时钟信号而工作。
    • 39. 发明授权
    • C-MOS thin film transistor device manufacturing method
    • C-MOS薄膜晶体管器件的制造方法
    • US5316960A
    • 1994-05-31
    • US78409
    • 1993-06-17
    • Hirofumi WatanabeNoriyuki Terao
    • Hirofumi WatanabeNoriyuki Terao
    • H01L21/84H01L21/265
    • H01L21/84Y10S148/137Y10S148/15
    • A method for manufacturing a C-MOS thin film transistor device has the steps of implanting the n-type impurity only in the upper layer portion of the source-drain section of the n-channel transistor by controlling implantation energy of the n-type impurity; implanting the p-type impurity in the source-drain section and the gate electrode of the p-channel transistor, and the source-drain section and the gate electrode of the n-channel transistor by controlling implantation energy of the p-type impurity; and activating the implanted n-type and p-type impurities in the source-drain section of the n-channel transistor, and activating the implanted p-type impurity in the source-drain section and the gate electrode of the p-channel transistor and gate electrode of the n-channel transistor. The n-type and the p-type may be respectively changed to the p-type and the n-type in the above construction.
    • 用于制造C-MOS薄膜晶体管器件的方法具有以下步骤:通过控制n型杂质的注入能量将n型杂质仅植入在n沟道晶体管的源极 - 漏极部分的上层部分中 ; 通过控制p型杂质的注入能量,将p型杂质注入到p沟道晶体管的源极 - 漏极部分和栅极电极以及n沟道晶体管的源极 - 漏极部分和栅极电极中; 以及激活n沟道晶体管的源极 - 漏极部分中注入的n型和p型杂质,以及激活p沟道晶体管的源 - 漏部分和栅电极中注入的p型杂质,以及 n沟道晶体管的栅电极。 在上述结构中,n型和p型可以分别变为p型和n型。