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    • 34. 发明授权
    • Software-based and hardware-based hybrid synthesizer
    • 基于软件和基于硬件的混合合成器
    • US5808221A
    • 1998-09-15
    • US723172
    • 1996-09-30
    • Gal AshourYoav MedanNaftaly Sharir
    • Gal AshourYoav MedanNaftaly Sharir
    • G10H1/02G10H1/00G10H7/00G10H7/02G10H7/08G10H1/08
    • G10H1/0075G10H7/004G10H2230/041
    • An audio synthesizer is disclosed for generating an analog or digital audio output in response to coded control instructions representing musical events, such as a MIDI data stream. The synthesizer has a general purpose computer portion with a CPU programmed to receive the control instructions and generate audio samples and a special purpose hardware portion for receiving the control instructions and generating the audio samples. The synthesizer also has a controller for directing the control instructions either to the general purpose computer portion or to the hardware portion to generate the audio samples; and means to combine the audio samples generated by the general purpose computer portion and the hardware portion to form an audio output which accords with the control instructions.
    • 公开了一种音频合成器,用于响应于表示诸如MIDI数据流的音乐事件的编码控制指令来产生模拟或数字音频输出。 合成器具有通用计算机部分,CPU被编程为接收控制指令并生成音频采样以及专用硬件部分,用于接收控制指令并产生音频采样。 合成器还具有用于将控制指令引导到通用计算机部分或硬件部分以产生音频样本的控制器; 以及将由通用计算机部分生成的音频样本与硬件部分组合以形成符合控制指令的音频输出的装置。
    • 36. 发明授权
    • Signal processor
    • 信号处理器
    • US5387910A
    • 1995-02-07
    • US1481
    • 1993-01-07
    • Yoav MedanUzi Shvadron
    • Yoav MedanUzi Shvadron
    • G06F3/05G06F17/17G10L21/04H03H17/00H03H17/02H03H17/06H03M1/00H04B14/04H03M1/66
    • H03H17/0642G06F17/17H03H17/0685
    • A signal processor is described for sampling rate conversion of a digitally sampled analog signal, the signal processor including an apparatus for generating an output sampled value for each output sampling instant, the output sampled value being equal to the input sampled value at the last input sampling instant if an input sampling instant has not occurred since the last output sampling instant and being calculated as an interpolation of input values at successive input sampling instants if an input sampling instant has occurred since the last output sampling instant. A virtual, analytic A/D-D/A conversion is employed using digital processing to convert from a given sampling rate to an arbitrary desired rate.
    • 描述信号处理器用于采样数字采样模拟信号的采样率转换,信号处理器包括用于为每个输出采样时刻产生输出采样值的装置,输出采样值等于最后输入采样时的输入采样值 如果自上一个输出采样时刻以来没有发生输入采样时刻,并且如果自上次输出采样时刻以来已经发生输入采样时刻,则在连续输入采样时刻的输入值的内插计算即时。 使用数字处理来使用虚拟的分析A / D-D / A转换,以从给定的采样率转换成任意所需的速率。
    • 37. 发明授权
    • Programmable DCVS logic circuits
    • 可编程DCVS逻辑电路
    • US5166547A
    • 1992-11-24
    • US711487
    • 1991-06-05
    • Jacquelin BabakanianJames W. DavisMark S. GarvinKim P. LiewYoav MedanNandor G. Thoma
    • Jacquelin BabakanianJames W. DavisMark S. GarvinKim P. LiewYoav MedanNandor G. Thoma
    • H01L21/82H01L23/525H01L27/118H03K19/0952H03K19/173
    • H01L23/5258H03K19/1735H03K19/1738H01L2924/0002H01L2924/3011
    • A basic tree construction, from which differential cascode voltage switch (DCVS) circuits having variable logic personality can be formed, contains n (>2) rows of differentially associated semiconductor device pairs spanned by n pairs of complementary input conductor leads, and a load circuit coupled to drain terminals of devices in the nth row. The nth row contains 2 device pairs and each other row contains 2.sup.i-1 device pairs (i=1, 2, . . . , n-1). Connections between source and drain terminals of devices in successive rows are predefined from the 1st to the n-1st row and variably definable between the n-1st and nth rows. Connections between input conductors and device gate terminals are predefined in each row other than the nth row, and variably definable in the nth row. Upon selectively defining a set of variable connections relative to the n-1st and nth rows the logic personality of the tree is selected to conform to any one of all possible functions of n variables. Logic function personalization is established in one embodiment by altering materials at discrete points in a space between n-1st and nth rows. In another embodiment, personalization is established by altering signals stored by latch devices in the space between the n-1st and nth rows which control gating device adjacently positioned to form conductive connections corresponding to those formed by altering materials in the first embodiment.
    • 可以形成具有可变逻辑特性的差分共源共栅电压开关(DCVS)电路的基本树结构包含由n对互补输入导体引线跨越的n(> 2)个由差分相关的半导体器件对构成的行,负载电路 耦合到第n行的器件的漏极端子。 第n行包含2个设备对,每行包含2i-1个设备对(i = 1,2,...,n-1)。 在连续行中的设备的源极和漏极端子之间的连接从第一行到第n行预定义,并且可以在第n-1行和第n行之间可变地定义。 输入导体和器件栅极端子之间的连接在除第n行以外的每行中预定义,并且在第n行中可变地定义。 在选择性地定义相对于第n-1和n行的一组可变连接时,选择树的逻辑个性以符合n个变量的所有可能函数中的任何一个。 在一个实施例中通过在第n-1和第n行之间的空间中的离散点处改变材料来建立逻辑功能个性化。 在另一个实施例中,通过在第n-1行和第n行之间的空间中改变由锁存装置存储的信号来建立个性化,所述信号控制门控装置相邻定位以形成对应于在第一实施例中通过改变材料形成的导电连接的导电连接。