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    • 32. 发明申请
    • Epitaxy silicon on insulator (ESOI)
    • 外延绝缘体硅(ESOI)
    • US20070298593A1
    • 2007-12-27
    • US11521667
    • 2006-09-15
    • Ming-Hua YuTze-Liang LeePang-Yen Tsai
    • Ming-Hua YuTze-Liang LeePang-Yen Tsai
    • H01L21/20H01L21/84H01L21/76
    • H01L29/0649H01L21/84H01L27/1203H01L29/045H01L29/517H01L29/6659H01L29/7843H01L29/7846
    • Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.
    • 提供了SOI衬底中具有STI区域的半导体器件的方法和结构。 半导体结构包括在衬底上形成的SOI外延岛。 该结构还包括围绕SOI岛的STI结构。 STI结构包括在衬底上的第二外延层和在第二外延层上的第二电介质层。 一种半导体制造方法包括在衬底上形成介电层并围绕延伸穿过介电层的隔离沟槽围绕衬底中的器件制造区域。 该方法还包括用第一外延层填充隔离沟槽,并在器件制造区域上方和第一外延层上形成第二外延层。 然后用绝缘电介质代替第一外延层的一部分,然后在器件制造区域内形成诸如晶体管的器件的第二外延层。
    • 37. 发明申请
    • Hybrid-strained sidewall spacer for CMOS process
    • 用于CMOS工艺的混合应变侧壁间隔件
    • US20060244074A1
    • 2006-11-02
    • US11119272
    • 2005-04-29
    • Chien-Hao ChenKai-Ting TsengTze-Liang Lee
    • Chien-Hao ChenKai-Ting TsengTze-Liang Lee
    • H01L29/76
    • H01L21/823807H01L21/823864H01L29/4966H01L29/7843
    • Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their gate electrode sidewall spacers are fabricated such that the orientation of the intrinsic stress in the sidewall spacers is opposite to the stress created in the channel. An embodiment includes selectively patterning a compressive stress layer to form NMOS electrode sidewall spacers, wherein the compressive NMOS electrode sidewall spacers create a tensile stress in a NMOS channel. Another embodiment comprises selectively patterning a tensile stress layer to form tensile PMOS electrode sidewall spacers, wherein the PMOS electrode sidewall spacers create a compressive stress in a PMOS channel. Still other embodiments of the invention provide a semiconductor device having strained sidewall spacers. In one embodiment, a spacer having an intrinsic stress comprising one of tensile and compressive corresponds to a channel stress that is the other of tensile and compressive.
    • 本发明的实施例提供一种半导体器件和制造方法。 MOS器件及其栅电极侧壁间隔件被制造成使得侧壁间隔物中的本征应力的取向与在通道中产生的应力相反。 一个实施例包括选择性地图案化压应力层以形成NMOS电极侧壁间隔物,其中压电NMOS电极侧壁间隔件在NMOS沟道中产生拉伸应力。 另一个实施例包括选择性地图案化拉伸应力层以形成拉伸PMOS电极侧壁间隔物,其中PMOS电极侧壁间隔件在PMOS沟道中产生压缩应力。 本发明的其它实施例提供了具有应变侧壁间隔物的半导体器件。 在一个实施例中,具有包括拉伸和压缩中的一个的本征应力的间隔物对应于作为拉伸和压缩的另一个的通道应力。
    • 38. 发明申请
    • Strained transistor with hybrid-strain inducing layer
    • 具有杂化应变诱导层的应变晶体管
    • US20060186470A1
    • 2006-08-24
    • US11062723
    • 2005-02-22
    • Chien-Hao ChenTze-Liang Lee
    • Chien-Hao ChenTze-Liang Lee
    • H01L29/76H01L29/94
    • H01L29/4983H01L29/66628H01L29/66636H01L29/7843
    • A semiconductor device having a hybrid-strained layer and a method of forming the same are discussed. The semiconductor device comprises: a gate dielectric over a substrate; a gate electrode over the gate dielectric; an optional pair of spacers along the sidewalls of the gate dielectric and the gate electrode; a source/drain region substantially aligned with an edge of the gate electrode; and a strained layer over the source/drain region, gate electrode, and spacers wherein the strained layer has a first portion and a second portion. The first portion of the strained layer is substantially over the source/drain region and has a first inherent strain. The second portion of the strained layer has at least a portion substantially over the gate electrode and the spacers and has a second inherent strain of the opposite type of the first strain.
    • 讨论了具有混合应变层的半导体器件及其形成方法。 半导体器件包括:衬底上的栅极电介质; 位于栅极电介质上的栅电极; 沿着栅极电介质和栅电极的侧壁的可选的一对间隔物; 源极/漏极区域,其基本上与栅电极的边缘对齐; 以及源极/漏极区域上的应变层,栅电极和间隔物,其中应变层具有第一部分和第二部分。 应变层的第一部分基本上在源极/漏极区域之上并且具有第一固有应变。 应变层的第二部分具有基本上在栅电极和间隔物上的至少一部分,并且具有相反类型的第一应变的第二固有应变。
    • 39. 发明申请
    • MOSFET device with localized stressor
    • 具有局部应力源的MOSFET器件
    • US20060125028A1
    • 2006-06-15
    • US11012413
    • 2004-12-15
    • Chien-Hao ChenDonald ChaoTze-Liang LeeShih-Chang Chen
    • Chien-Hao ChenDonald ChaoTze-Liang LeeShih-Chang Chen
    • H01L29/76H01L21/8238
    • H01L29/7833H01L29/6659H01L29/7843
    • A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.
    • 提供了具有局部应力源的金属氧化物半导体场效应晶体管(MOSFET)。 根据本发明的实施例,晶体管包括源/漏区上的高应力膜,但不在栅电极上。 高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。 在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源/漏区的晶体管,在栅电极和源/漏区上形成高应力膜,然后除去 高应力膜位于栅电极之上,从而使高应力膜位于源极/漏极区之上。 接触蚀刻停止层可以形成在晶体管上。