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31. 发明申请

US20080146012A1 NOVEL METHOD TO ADJUST WORK FUNCTION BY PLASMA ASSISTED METAL INCORPORATED DIELECTRIC 审中-公开
标题翻译：通过等离子体辅助金属合成电介质调整工作功能的新方法
公开(公告)号：US20080146012A1
公开(公告)日：2008-06-19
申请号：US11695227
申请日：2007-04-02
申请人： Wenli Lin , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee , Mong-Song Liang
发明人： Wenli Lin , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee , Mong-Song Liang
IPC分类号： H01L21/3205 , H01L21/31
CPC分类号： H01L21/3115 , H01L21/28185 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric on a substrate; introducing metal dopants into the gate dielectric; annealing the gate dielectric; and forming a gate electrode on the gate dielectric.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成栅极电介质; 将金属掺杂剂引入栅极电介质中; 退火栅电介质; 以及在栅极电介质上形成栅电极。

32. 发明申请

US20070298593A1 Epitaxy silicon on insulator (ESOI) 有权
标题翻译：外延绝缘体硅（ESOI）
公开(公告)号：US20070298593A1
公开(公告)日：2007-12-27
申请号：US11521667
申请日：2006-09-15
申请人： Ming-Hua Yu , Tze-Liang Lee , Pang-Yen Tsai
发明人： Ming-Hua Yu , Tze-Liang Lee , Pang-Yen Tsai
IPC分类号： H01L21/20 , H01L21/84 , H01L21/76
CPC分类号： H01L29/0649 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/517 , H01L29/6659 , H01L29/7843 , H01L29/7846
摘要： Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.
摘要翻译：提供了SOI衬底中具有STI区域的半导体器件的方法和结构。半导体结构包括在衬底上形成的SOI外延岛。该结构还包括围绕SOI岛的STI结构。 STI结构包括在衬底上的第二外延层和在第二外延层上的第二电介质层。一种半导体制造方法包括在衬底上形成介电层并围绕延伸穿过介电层的隔离沟槽围绕衬底中的器件制造区域。该方法还包括用第一外延层填充隔离沟槽，并在器件制造区域上方和第一外延层上形成第二外延层。然后用绝缘电介质代替第一外延层的一部分，然后在器件制造区域内形成诸如晶体管的器件的第二外延层。

33. 发明授权

US07186662B2 Method for forming a hard mask for gate electrode patterning and corresponding device 有权
标题翻译：用于形成用于栅极电极图案化的硬掩模和相应装置的方法
公开(公告)号：US07186662B2
公开(公告)日：2007-03-06
申请号：US10964841
申请日：2004-10-13
申请人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
IPC分类号： H01L21/461
CPC分类号： H01L21/28123 , H01L21/0217 , H01L21/28035 , H01L21/31608 , H01L21/3185
摘要： A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch rate of silicon oxide. The polysilicon can then be patterned using the hardmask and the hardmask can be removed using hydrofluoric acid.
摘要翻译：公开了一种在半导体器件中形成用于栅电极图案化的硬掩模的方法。该方法包括提供待蚀刻并在多晶硅层上形成的多晶硅层，与氧化硅的蚀刻速率相比，具有对氢氟酸的蚀刻速率相对较高的氮化物硬掩模。然后可以使用硬掩模对多晶硅进行图案化，并且可以使用氢氟酸去除硬掩模。

34. 发明申请

US20070037326A1 Shallow source/drain regions for CMOS transistors 审中-公开
标题翻译： CMOS晶体管的浅源极/漏极区域
公开(公告)号：US20070037326A1
公开(公告)日：2007-02-15
申请号：US11200374
申请日：2005-08-09
申请人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee
发明人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee
IPC分类号： H01L21/84
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/6659 , H01L29/66772 , H01L29/7833
摘要： A transistor having shallow, high-dopant concentration source/drain regions is provided. A gate electrode is formed on a substrate, and the source/drain regions of the substrate are transformed into an amorphous state by, for example, implanting Si, Ge, Xe, In, Ar, Kr, Rn, a combination thereof, or the like ions. A co-implantation process is performed to implant ions of C, N, F, a combination thereof, or the like in the source/drain regions. Thereafter, one or more implants may be performed to form the LDD and source/drain regions and the substrate is recrystallized. The amorphous regions and the co-implantation regions effectively confine or reduce the diffusion of the ions used to form the LDD and source/drain regions.
摘要翻译：提供具有浅掺杂浓度源/漏区的晶体管。在基板上形成栅电极，通过例如注入Si，Ge，Xe，In，Ar，Kr，Rn及其组合，将基板的源极/漏极区域变换为非晶态，或像离子。执行共注入工艺以在源极/漏极区域中注入C，N，F，它们的组合等的离子。此后，可以执行一个或多个植入物以形成LDD和源极/漏极区域，并且衬底被重结晶。非晶区域和共注入区域有效地限制或减少用于形成LDD和源极/漏极区域的离子的扩散。

35. 发明授权

US07157350B2 Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration 有权
公开(公告)号：US07157350B2
公开(公告)日：2007-01-02
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

36. 发明申请

US20060286758A1 Super anneal for process induced strain modulation 有权
公开(公告)号：US20060286758A1
公开(公告)日：2006-12-21
申请号：US11199011
申请日：2005-08-08
申请人： Mong Liang , Chien-Hao Chen , Chun-Feng Nieh , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
发明人： Mong Liang , Chien-Hao Chen , Chun-Feng Nieh , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/7624 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.

37. 发明申请

US20060244074A1 Hybrid-strained sidewall spacer for CMOS process 审中-公开
标题翻译：用于CMOS工艺的混合应变侧壁间隔件
公开(公告)号：US20060244074A1
公开(公告)日：2006-11-02
申请号：US11119272
申请日：2005-04-29
申请人： Chien-Hao Chen , Kai-Ting Tseng , Tze-Liang Lee
发明人： Chien-Hao Chen , Kai-Ting Tseng , Tze-Liang Lee
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/4966 , H01L29/7843
摘要： Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their gate electrode sidewall spacers are fabricated such that the orientation of the intrinsic stress in the sidewall spacers is opposite to the stress created in the channel. An embodiment includes selectively patterning a compressive stress layer to form NMOS electrode sidewall spacers, wherein the compressive NMOS electrode sidewall spacers create a tensile stress in a NMOS channel. Another embodiment comprises selectively patterning a tensile stress layer to form tensile PMOS electrode sidewall spacers, wherein the PMOS electrode sidewall spacers create a compressive stress in a PMOS channel. Still other embodiments of the invention provide a semiconductor device having strained sidewall spacers. In one embodiment, a spacer having an intrinsic stress comprising one of tensile and compressive corresponds to a channel stress that is the other of tensile and compressive.
摘要翻译：本发明的实施例提供一种半导体器件和制造方法。 MOS器件及其栅电极侧壁间隔件被制造成使得侧壁间隔物中的本征应力的取向与在通道中产生的应力相反。一个实施例包括选择性地图案化压应力层以形成NMOS电极侧壁间隔物，其中压电NMOS电极侧壁间隔件在NMOS沟道中产生拉伸应力。另一个实施例包括选择性地图案化拉伸应力层以形成拉伸PMOS电极侧壁间隔物，其中PMOS电极侧壁间隔件在PMOS沟道中产生压缩应力。本发明的其它实施例提供了具有应变侧壁间隔物的半导体器件。在一个实施例中，具有包括拉伸和压缩中的一个的本征应力的间隔物对应于作为拉伸和压缩的另一个的通道应力。

38. 发明申请

US20060186470A1 Strained transistor with hybrid-strain inducing layer 有权
标题翻译：具有杂化应变诱导层的应变晶体管
公开(公告)号：US20060186470A1
公开(公告)日：2006-08-24
申请号：US11062723
申请日：2005-02-22
申请人： Chien-Hao Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Tze-Liang Lee
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/4983 , H01L29/66628 , H01L29/66636 , H01L29/7843
摘要： A semiconductor device having a hybrid-strained layer and a method of forming the same are discussed. The semiconductor device comprises: a gate dielectric over a substrate; a gate electrode over the gate dielectric; an optional pair of spacers along the sidewalls of the gate dielectric and the gate electrode; a source/drain region substantially aligned with an edge of the gate electrode; and a strained layer over the source/drain region, gate electrode, and spacers wherein the strained layer has a first portion and a second portion. The first portion of the strained layer is substantially over the source/drain region and has a first inherent strain. The second portion of the strained layer has at least a portion substantially over the gate electrode and the spacers and has a second inherent strain of the opposite type of the first strain.
摘要翻译：讨论了具有混合应变层的半导体器件及其形成方法。半导体器件包括：衬底上的栅极电介质; 位于栅极电介质上的栅电极; 沿着栅极电介质和栅电极的侧壁的可选的一对间隔物; 源极/漏极区域，其基本上与栅电极的边缘对齐; 以及源极/漏极区域上的应变层，栅电极和间隔物，其中应变层具有第一部分和第二部分。应变层的第一部分基本上在源极/漏极区域之上并且具有第一固有应变。应变层的第二部分具有基本上在栅电极和间隔物上的至少一部分，并且具有相反类型的第一应变的第二固有应变。

39. 发明申请

US20060125028A1 MOSFET device with localized stressor 有权
标题翻译：具有局部应力源的MOSFET器件
公开(公告)号：US20060125028A1
公开(公告)日：2006-06-15
申请号：US11012413
申请日：2004-12-15
申请人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/7833 , H01L29/6659 , H01L29/7843
摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.
摘要翻译：提供了具有局部应力源的金属氧化物半导体场效应晶体管（MOSFET）。根据本发明的实施例，晶体管包括源/漏区上的高应力膜，但不在栅电极上。高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源/漏区的晶体管，在栅电极和源/漏区上形成高应力膜，然后除去高应力膜位于栅电极之上，从而使高应力膜位于源极/漏极区之上。接触蚀刻停止层可以形成在晶体管上。

40. 发明申请

US20050253194A1 SOI-like structure in a bulk semiconductor substrate and method of forming same 有权
标题翻译：体半导体衬底中的SOI类结构及其形成方法
公开(公告)号：US20050253194A1
公开(公告)日：2005-11-17
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/324 , H01L21/762 , H01L27/01 , H01L27/12
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

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