专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20110076823A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110076823A1
公开(公告)日：2011-03-31
申请号：US12568657
申请日：2009-09-28
申请人： Huang-Yi Lin , Jiun-Hung Shen , Chi-Horn Pai , Yi-Chung Sheng , Shih-Chieh Hsu
发明人： Huang-Yi Lin , Jiun-Hung Shen , Chi-Horn Pai , Yi-Chung Sheng , Shih-Chieh Hsu
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/6656 , H01L29/6659 , H01L29/7847
摘要： A method for making a semiconductor MOS device is provided. A gate structure is formed on a substrate. A source and a drain are formed in the substrate on both sides of the gate structure. The substrate is then subjected to a pre-amorphization implant (PAI) process. A transitional stress layer is then formed on the substrate. Thereafter, a laser anneal with a first temperature is performed. After the laser anneal, a rapid thermal process is performed with a second temperature that is lower than the first temperature. Subsequently, the transitional stress layer is removed.
摘要翻译：提供了制造半导体MOS器件的方法。在基板上形成栅极结构。源极和漏极形成在栅极结构两侧的衬底中。然后将基材进行预非晶化植入（PAI）工艺。然后在衬底上形成过渡应力层。此后，进行具有第一温度的激光退火。在激光退火之后，以低于第一温度的第二温度进行快速热处理。随后，去除过渡应力层。

32. 发明申请

US20100297791A1 METHOD FOR INSPECTING PHOTORESIST PATTERN 有权
标题翻译：检查光栅图案的方法
公开(公告)号：US20100297791A1
公开(公告)日：2010-11-25
申请号：US12468063
申请日：2009-05-19
申请人： Chia-Chen Sun , Yi-Chung Sheng , Sheng-Yuan Hsueh
发明人： Chia-Chen Sun , Yi-Chung Sheng , Sheng-Yuan Hsueh
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , G03F7/70658 , H01L22/14
摘要： A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate is doped by using the photoresist pattern, and a PN junction exists in the first doping region. Thereafter, a current passing through the PN junction is tested to inspect the photoresist pattern.
摘要翻译：公开了一种用于检查光致抗蚀剂图案的方法。首先，提供具有第一掺杂区域的衬底。然后，形成光致抗蚀剂以覆盖基板。之后，将光致抗蚀剂图案化以形成光致抗蚀剂图案。之后，通过使用光致抗蚀剂图案来掺杂衬底，并且PN结存在于第一掺杂区域中。此后，测试通过PN结的电流，以检查光刻胶图案。

33. 发明授权

US07550356B2 Method of fabricating strained-silicon transistors 有权
标题翻译：制造应变硅晶体管的方法
公开(公告)号：US07550356B2
公开(公告)日：2009-06-23
申请号：US11164177
申请日：2005-11-14
申请人： Cheng-Tung Huang , Chia-Wen Liang , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Cheng-Tung Huang , Chia-Wen Liang , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/6653 , Y10S438/938
摘要： A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.
摘要翻译：制造应变硅晶体管的方法包括：提供半导体衬底，其中半导体衬底包括栅极，至少间隔物和源极/漏极区域; 执行第一快速热退火（RTA）工艺; 去除间隔物并在栅极和源极/漏极区域的表面上形成高拉伸应力膜; 并进行第二快速热退火处理。

34. 发明申请

US20080093627A1 SEMICONDUCTOR MOS TRANSISTOR DEVICE AND METHOD FOR MAKING THE SAME 有权
标题翻译：半导体MOS晶体管器件及其制造方法
公开(公告)号：US20080093627A1
公开(公告)日：2008-04-24
申请号：US11927642
申请日：2007-10-29
申请人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L29/778
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7843
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
摘要翻译：公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。栅介质层形成在衬底的有源区上。在栅极电介质层上形成栅电极。栅电极具有垂直侧壁和顶表面。衬套形成在栅电极的垂直侧壁上。在衬套上形成氮化物间隔物。进行离子注入以形成源极/漏极区域。在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。去除氮化物间隔物。与衬垫相邻的氮化物覆盖层被沉积。氮化物盖层具有特定的应力状态。

35. 发明申请

US20070087542A1 METHOD OF FORMING A SILICIDE 审中-公开
标题翻译：形成硅酮的方法
公开(公告)号：US20070087542A1
公开(公告)日：2007-04-19
申请号：US11567220
申请日：2006-12-06
申请人： Jen-Hong Huang , Nien-Chung Li , Yi-Chung Sheng , Chun-Chia Chen
发明人： Jen-Hong Huang , Nien-Chung Li , Yi-Chung Sheng , Chun-Chia Chen
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/665 , H01L29/6653 , H01L29/6656
摘要： At least one gate electrode is formed on a substrate. A first dielectric layer and a second dielectric layer are formed on the gate electrode, respectively. A portion of the second dielectric layer is removed to form a spacer on either side of the gate electrode. A portion of the first dielectric layer is removed to form a notch between the gate electrode and the spacer, the notch having an aspect ratio greater than 1. A self-aligned silicide process is performed to form a silicide on exposed surfaces of the gate electrode and the first dielectric layer underneath the notch.
摘要翻译：在基板上形成至少一个栅电极。分别在栅电极上形成第一电介质层和第二电介质层。去除第二电介质层的一部分以在栅电极的任一侧上形成间隔物。去除第一电介质层的一部分以在栅电极和间隔物之间形成凹口，凹口具有大于1的纵横比。进行自对准硅化物工艺以在栅电极的暴露表面上形成硅化物和凹口下方的第一介电层。

36. 发明授权

US6127212A Method of forming a CMOS transistor 有权
标题翻译：形成CMOS晶体管的方法
公开(公告)号：US6127212A
公开(公告)日：2000-10-03
申请号：US488811
申请日：2000-01-21
申请人： Chin-Lan Chen , Cheng-Tung Huang , Shih-Chieh Hsu , Yi-Chung Sheng
发明人： Chin-Lan Chen , Cheng-Tung Huang , Shih-Chieh Hsu , Yi-Chung Sheng
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864
摘要： The present invention provides a method for forming a CMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a substrate, a first gate positioned on the substrate being used to form a PMOS transistor of the CMOS transistor, and a second gate positioned on the substrate being used to form an NMOS transistor of the CMOS transistor. First spacers are formed on both lateral surfaces of the first gate and of the second gate. A first ion implantation process is performed to form a pair of first doped regions in the substrate, oppositely adjacent to the first gate, the pair of first doped regions to serve as heavy doped drain (HDD) of the PMOS transistor. Then the thickness of the first spacers is reduced. A second ion implantation process is performed to form a pair of second doped regions in the substrate, oppositely adjacent to the second gate, the pair of second doped regions to serve as the HDD of the NMOS transistor. Second spacers are then formed covering each first spacer. Finally, sources/drains for the PMOS transistor and the NMOS transistor are formed in the substrate, oppositely adjacent to the first gate and the second gate.
摘要翻译：本发明提供一种在半导体晶片上形成CMOS晶体管的方法。半导体晶片包括衬底，位于衬底上的第一栅极用于形成CMOS晶体管的PMOS晶体管，以及位于衬底上的第二栅极，用于形成CMOS晶体管的NMOS晶体管。第一间隔件形成在第一栅极和第二栅极的两个侧表面上。执行第一离子注入工艺以在衬底中形成一对与第一栅极相对的第一掺杂区域，该对第一掺杂区域用作PMOS晶体管的重掺杂漏极（HDD）。然后减小第一间隔物的厚度。执行第二离子注入工艺以在衬底中形成与第二栅极相对的一对第二掺杂区域，该对第二掺杂区域用作NMOS晶体管的HDD。然后形成覆盖每个第一间隔物的第二间隔物。最后，PMOS晶体管和NMOS晶体管的源极/漏极形成在与第一栅极和第二栅极相对的衬底中。

37. 发明授权

US5859460A Tri-state read-only memory device and method for fabricating the same 失效
标题翻译：三态只读存储器件及其制造方法
公开(公告)号：US5859460A
公开(公告)日：1999-01-12
申请号：US839497
申请日：1997-04-14
申请人： Kuan-Cheng Su , Chen-Hui Chung , Yi-Chung Sheng
发明人： Kuan-Cheng Su , Chen-Hui Chung , Yi-Chung Sheng
IPC分类号： G11C11/56 , H01L21/8246 , H01L27/112 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/1126 , G11C11/56 , G11C11/5692 , H01L27/112
摘要： A tri-state read-only memory device and its fabrication method are disclosed herein. After a plurality of word lines are formed and spaced apart in parallel through patterning by a shielding layer, insulating blocks are formed to fill the trenches among the word lines. Then removing the shielding layer, sidewalls, of the insulating blocks are revealed, and spacers are formed on the sidewalls thereof. The spacers above the first state regions are removed to form the conductive width of the channel regions in three forms. By merely applying one code-implantation, the ROM device are coded into on of three states at the same time. In addition, the disposition of the insulating blocks by liquid-phase deposition prevents the misalignment that often occurs with the conventional method.
摘要翻译：本文公开了三态只读存储器件及其制造方法。在通过屏蔽层构图形成多个字线并平行间隔开之后，形成绝缘块以填充字线之间的沟槽。然后，去除绝缘块的屏蔽层侧壁，并且在其侧壁上形成间隔物。去除第一状态区之上的间隔物以形成三种形式的沟道区的导电宽度。通过仅仅应用一个代码注入，ROM设备被同时编码成三种状态。此外，通过液相沉积的绝缘块的布置防止了常规方法经常发生的不对准。

38. 发明授权

US5693551A Method for fabricating a tri-state read-only memory device 失效
标题翻译：制造三态只读存储器件的方法
公开(公告)号：US5693551A
公开(公告)日：1997-12-02
申请号：US530575
申请日：1995-09-19
申请人： Kuan-Cheng Su , Chen-Hui Chung , Yi-Chung Sheng
发明人： Kuan-Cheng Su , Chen-Hui Chung , Yi-Chung Sheng
IPC分类号： G11C11/56 , H01L21/8246 , H01L27/112
CPC分类号： H01L27/1126 , G11C11/56 , G11C11/5692 , H01L27/112
摘要： A tri-state read-only memory device and its fabrication method are disclosed herein. After a plurality of word lines are formed and spaced apart in parallel through patterning by a shielding layer, insulating blocks are formed to fill the trenches among the word lines. Then removing the shielding layer, sidewalls of the insulating blocks are revealed, and spacers are formed on the sidewalls thereof. The spacers above the first state regions are removed to form the conductive width of the channel regions in three forms. By merely applying one code-implantation, the ROM device are coded into on of three states at the same time. In addition, the disposition of the insulating blocks by liquid-phase deposition prevents the misalignment that often occurs with the conventional method.
摘要翻译：本文公开了三态只读存储器件及其制造方法。在通过屏蔽层构图形成多个字线并平行间隔开之后，形成绝缘块以填充字线之间的沟槽。然后去除屏蔽层，揭示绝缘块的侧壁，并在其侧壁上形成间隔物。去除第一状态区之上的间隔物以形成三种形式的沟道区的导电宽度。通过仅仅应用一个代码注入，ROM设备被同时编码成三种状态。此外，通过液相沉积的绝缘块的布置防止了常规方法经常发生的不对准。

39. 发明授权

US5668030A Process for making identification alphanumeric code markings for mask ROM devices 失效
标题翻译：用于为掩模ROM设备识别字母数字代码标记的过程
公开(公告)号：US5668030A
公开(公告)日：1997-09-16
申请号：US524549
申请日：1995-09-07
申请人： Chen-Hui Chung , Kuan-Cheng Su , Yi-Chung Sheng
发明人： Chen-Hui Chung , Kuan-Cheng Su , Yi-Chung Sheng
IPC分类号： H01L21/8246 , H01L23/544
CPC分类号： H01L27/1126 , H01L23/544 , H01L2223/54453 , H01L2223/54493 , H01L2924/0002
摘要： A process for fabricating identification alphanumeric code markings on the substrate of mask ROM devices is disclosed. The fabrication process comprises first forming a deposited layer on the substrate of the mask ROM device. A photoresist layer is then formed on the deposited layer. A photomask layer by is then shaped by forming a pattern on the photoresist layer that reveals the channel regions of the memory cell transistors to be programmed into the blocking state, as well as reveals the graphical pattern of the alphanumeric code marking. An etching procedure then removes the portion of the deposited layer revealing the graphical pattern of the alphanumeric code markings. The photomask layer is then removed. A code implantation procedure may precede or follow the etching procedure to facilitate the programming of the memory cells of the mask ROM device.
摘要翻译：公开了一种用于在掩模ROM器件的衬底上制造识别字母数字代码标记的过程。制造工艺包括首先在掩模ROM器件的衬底上形成沉积层。然后在沉积层上形成光致抗蚀剂层。然后通过在光致抗蚀剂层上形成图案来形成光掩模层，该图案将存储单元晶体管的通道区域显示为被编程成阻塞状态，以及揭示字母数字代码标记的图形图案。然后，蚀刻过程去除沉积层的部分，露出字母数字代码标记的图形图案。然后去除光掩模层。代码注入过程可以在蚀刻过程之前或之后，以便于掩模ROM器件的存储器单元的编程。

40. 发明授权

US5597753A CVD oxide coding method for ultra-high density mask read-only-memory (ROM) 失效
标题翻译：用于超高密度掩模只读存储器（ROM）的CVD氧化物编码方法
公开(公告)号：US5597753A
公开(公告)日：1997-01-28
申请号：US364318
申请日：1994-12-27
申请人： Shing-Ren Sheu , Kuan-Cheng Su , Chen-Hui Chung , Yi-Chung Sheng
发明人： Shing-Ren Sheu , Kuan-Cheng Su , Chen-Hui Chung , Yi-Chung Sheng
IPC分类号： H01L21/8246
CPC分类号： H01L27/11246 , Y10S438/981
摘要： An improved Read-Only-Memory (ROM) structure and a method of manufacturing said ROM device structure having an ultra-high-density of coded ROM cells, was achieved. The array of programmed ROM cells are composed of a single field effect transistor (FET) in each ROM cell. The improved ROM process utilizes the patterning of a ROM code insulating layer over each coded FET (cell) that is selected to remain in an off-state (nonconducting) when a gate voltage is applied. The remaining FETs (cells) have a thin gate oxide which switch to the on-state (conducting) when a gate voltage is applied. The thick ROM code insulating layer eliminates the need to code the FETs in the ROM memory cells by conventional high dose ion implantation. This eliminated the counter-doping of the buried bit lines by the implantation allowing for much tighter ground rules for the spacing between buried bit line. The elimination of the implant also reduces substantially the stand-by leakage current that is so important in battery operated electronic equipment, such as lap-top computers. The gate capacitance of the off-state cells is also substantially reduced because of the thick insulating layer, thereby reducing the RC time delay in the word lines and improving circuit performance.
摘要翻译：实现了改进的只读存储器（ROM）结构和制造具有超高密度编码ROM单元的所述ROM器件结构的方法。编程ROM单元的阵列由每个ROM单元中的单个场效应晶体管（FET）构成。改进的ROM处理利用在施加栅极电压时选择为保持在截止状态（非导通）的每个编码的FET（单元）上的ROM代码绝缘层的图案化。当施加栅极电压时，剩余的FET（单元）具有薄的栅极氧化物，其切换到导通状态（导通）。粗ROM代码绝缘层消除了通过常规高剂量离子注入对ROM存储单元中的FET进行编码的需要。这通过注入消除了掩埋位线的反掺杂，允许掩埋位线之间的间隔更紧密的基本规则。植入物的消除也大大降低了备用泄漏电流，这在电池供电的电子设备如笔记本电脑中如此重要。由于厚的绝缘层，断态单元的栅极电容也显着减小，从而减小了字线中的RC时间延迟并提高了电路性能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式