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1. 发明申请

US20090137089A1 SEMICONDUCTOR MOS TRANSISTOR DEVICE AND METHOD FOR MAKING THE SAME 有权
标题翻译：半导体MOS晶体管器件及其制造方法
公开(公告)号：US20090137089A1
公开(公告)日：2009-05-28
申请号：US12366625
申请日：2009-02-05
申请人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7843
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
摘要翻译：公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。栅介质层形成在衬底的有源区上。在栅极电介质层上形成栅电极。栅电极具有垂直侧壁和顶表面。衬套形成在栅电极的垂直侧壁上。在衬套上形成氮化物间隔物。进行离子注入以形成源极/漏极区域。在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。去除氮化物间隔物。与衬垫相邻的氮化物覆盖层被沉积。氮化物盖层具有特定的应力状态。

2. 发明授权

US07342284B2 Semiconductor MOS transistor device and method for making the same 有权
标题翻译：半导体MOS晶体管器件及其制造方法
公开(公告)号：US07342284B2
公开(公告)日：2008-03-11
申请号：US11307660
申请日：2006-02-16
申请人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7843
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
摘要翻译：公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。栅介质层形成在衬底的有源区上。在栅极电介质层上形成栅电极。栅电极具有垂直侧壁和顶表面。衬套形成在栅电极的垂直侧壁上。在衬套上形成氮化物间隔物。进行离子注入以形成源极/漏极区域。在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。去除氮化物间隔物。与衬垫相邻的氮化物覆盖层被沉积。氮化物盖层具有特定的应力状态。

3. 发明申请

US20080093627A1 SEMICONDUCTOR MOS TRANSISTOR DEVICE AND METHOD FOR MAKING THE SAME 有权
标题翻译：半导体MOS晶体管器件及其制造方法
公开(公告)号：US20080093627A1
公开(公告)日：2008-04-24
申请号：US11927642
申请日：2007-10-29
申请人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L29/778
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7843
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
摘要翻译：公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。栅介质层形成在衬底的有源区上。在栅极电介质层上形成栅电极。栅电极具有垂直侧壁和顶表面。衬套形成在栅电极的垂直侧壁上。在衬套上形成氮化物间隔物。进行离子注入以形成源极/漏极区域。在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。去除氮化物间隔物。与衬垫相邻的氮化物覆盖层被沉积。氮化物盖层具有特定的应力状态。

4. 发明授权

US07749833B2 Semiconductor MOS transistor device and method for making the same 有权
标题翻译：半导体MOS晶体管器件及其制造方法
公开(公告)号：US07749833B2
公开(公告)日：2010-07-06
申请号：US12366625
申请日：2009-02-05
申请人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7843
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
摘要翻译：公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。栅介质层形成在衬底的有源区上。在栅极电介质层上形成栅电极。栅电极具有垂直侧壁和顶表面。衬套形成在栅电极的垂直侧壁上。在衬套上形成氮化物间隔物。进行离子注入以形成源极/漏极区域。在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。去除氮化物间隔物。与衬垫相邻的氮化物覆盖层被沉积。氮化物盖层具有特定的应力状态。

5. 发明授权

US07508053B2 Semiconductor MOS transistor device and method for making the same 有权
标题翻译：半导体MOS晶体管器件及其制造方法
公开(公告)号：US07508053B2
公开(公告)日：2009-03-24
申请号：US11927642
申请日：2007-10-29
申请人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L23/58
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7843
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
摘要翻译：公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。栅介质层形成在衬底的有源区上。在栅极电介质层上形成栅电极。栅电极具有垂直侧壁和顶表面。衬套形成在栅电极的垂直侧壁上。在衬套上形成氮化物间隔物。进行离子注入以形成源极/漏极区域。在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。去除氮化物间隔物。与衬垫相邻的氮化物覆盖层被沉积。氮化物盖层具有特定的应力状态。

6. 发明申请

US20070187727A1 SEMICONDUCTOR MOS TRANSISTOR DEVICE AND METHOD FOR MAKING THE SAME 有权
标题翻译：半导体MOS晶体管器件及其制造方法
公开(公告)号：US20070187727A1
公开(公告)日：2007-08-16
申请号：US11307660
申请日：2006-02-16
申请人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Shyh-Fann Ting , Cheng-Tung Huang , Wen-Han Hung , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L29/80
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7843
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
摘要翻译：公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。栅介质层形成在衬底的有源区上。在栅极电介质层上形成栅电极。栅电极具有垂直侧壁和顶表面。衬套形成在栅电极的垂直侧壁上。在衬套上形成氮化物间隔物。进行离子注入以形成源极/漏极区域。在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。去除氮化物间隔物。与衬垫相邻的氮化物覆盖层被沉积。氮化物盖层具有特定的应力状态。

7. 发明授权

US07550356B2 Method of fabricating strained-silicon transistors 有权
标题翻译：制造应变硅晶体管的方法
公开(公告)号：US07550356B2
公开(公告)日：2009-06-23
申请号：US11164177
申请日：2005-11-14
申请人： Cheng-Tung Huang , Chia-Wen Liang , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Cheng-Tung Huang , Chia-Wen Liang , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/6653 , Y10S438/938
摘要： A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.
摘要翻译：制造应变硅晶体管的方法包括：提供半导体衬底，其中半导体衬底包括栅极，至少间隔物和源极/漏极区域; 执行第一快速热退火（RTA）工艺; 去除间隔物并在栅极和源极/漏极区域的表面上形成高拉伸应力膜; 并进行第二快速热退火处理。

8. 发明申请

US20070111416A1 Method of fabricating strained-silicon transistors 有权
标题翻译：制造应变硅晶体管的方法
公开(公告)号：US20070111416A1
公开(公告)日：2007-05-17
申请号：US11164177
申请日：2005-11-14
申请人： Cheng-Tung Huang , Chia-Wen Liang , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
发明人： Cheng-Tung Huang , Chia-Wen Liang , Tzyy-Ming Cheng , Tzer-Min Shen , Yi-Chung Sheng
IPC分类号： H01L21/8234 , H01L21/425 , H01L21/336
CPC分类号： H01L29/7843 , H01L29/6653 , Y10S438/938
摘要： A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.
摘要翻译：制造应变硅晶体管的方法包括：提供半导体衬底，其中半导体衬底包括栅极，至少间隔物和源极/漏极区域; 执行第一快速热退火（RTA）工艺; 去除间隔物并在栅极和源极/漏极区域的表面上形成高拉伸应力膜; 并进行第二快速热退火处理。

9. 发明授权

US06544849B2 Method of fabricating semiconductor device for preventing polysilicon line being damaged during removal of photoresist 有权
公开(公告)号：US06544849B2
公开(公告)日：2003-04-08
申请号：US09852254
申请日：2001-05-09
申请人： Shih-Chieh Hsu , Yi-Chung Sheng , Chang-Chi Huang , Sheng-Hao Lin , Cheng-Tung Huang
发明人： Shih-Chieh Hsu , Yi-Chung Sheng , Chang-Chi Huang , Sheng-Hao Lin , Cheng-Tung Huang
IPC分类号： H01L218234
CPC分类号： H01L21/823425
摘要： A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device. Since the offset spacers are formed on the sidewalls of the polysilicon lines before the photoresist layer is removed, the offset spacers can protect the polysilicon lines from being broken.

10. 发明授权

US6127212A Method of forming a CMOS transistor 有权
标题翻译：形成CMOS晶体管的方法
公开(公告)号：US6127212A
公开(公告)日：2000-10-03
申请号：US488811
申请日：2000-01-21
申请人： Chin-Lan Chen , Cheng-Tung Huang , Shih-Chieh Hsu , Yi-Chung Sheng
发明人： Chin-Lan Chen , Cheng-Tung Huang , Shih-Chieh Hsu , Yi-Chung Sheng
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864
摘要： The present invention provides a method for forming a CMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a substrate, a first gate positioned on the substrate being used to form a PMOS transistor of the CMOS transistor, and a second gate positioned on the substrate being used to form an NMOS transistor of the CMOS transistor. First spacers are formed on both lateral surfaces of the first gate and of the second gate. A first ion implantation process is performed to form a pair of first doped regions in the substrate, oppositely adjacent to the first gate, the pair of first doped regions to serve as heavy doped drain (HDD) of the PMOS transistor. Then the thickness of the first spacers is reduced. A second ion implantation process is performed to form a pair of second doped regions in the substrate, oppositely adjacent to the second gate, the pair of second doped regions to serve as the HDD of the NMOS transistor. Second spacers are then formed covering each first spacer. Finally, sources/drains for the PMOS transistor and the NMOS transistor are formed in the substrate, oppositely adjacent to the first gate and the second gate.
摘要翻译：本发明提供一种在半导体晶片上形成CMOS晶体管的方法。半导体晶片包括衬底，位于衬底上的第一栅极用于形成CMOS晶体管的PMOS晶体管，以及位于衬底上的第二栅极，用于形成CMOS晶体管的NMOS晶体管。第一间隔件形成在第一栅极和第二栅极的两个侧表面上。执行第一离子注入工艺以在衬底中形成一对与第一栅极相对的第一掺杂区域，该对第一掺杂区域用作PMOS晶体管的重掺杂漏极（HDD）。然后减小第一间隔物的厚度。执行第二离子注入工艺以在衬底中形成与第二栅极相对的一对第二掺杂区域，该对第二掺杂区域用作NMOS晶体管的HDD。然后形成覆盖每个第一间隔物的第二间隔物。最后，PMOS晶体管和NMOS晶体管的源极/漏极形成在与第一栅极和第二栅极相对的衬底中。

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