会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 31. 发明授权
    • Ouput buffer circuit
    • 输出缓冲电路
    • US06608505B2
    • 2003-08-19
    • US09795884
    • 2001-02-28
    • Nobuaki Tsuji
    • Nobuaki Tsuji
    • H03K300
    • H03K17/167H03K17/164H03K19/0013H03K19/01721
    • An output buffer circuit is provided, which is capable of obtaining a large drive power when the level of an input signal changes, while allowing a through current to flow in suppressed amounts. A first P-channel MOS transistor and a first N-channel MOS transistor are connected in series with a power supply. The pair of transistors are exclusively switched on and off by an input signal such that the first and second switching elements are not simultaneously on or off, to deliver an output signal corresponding to the input signal, from a common junction between the first and second switching elements. A second P-channel MOS transistor is connected in parallel with the first P-channel MOS transistor as an auxiliary transistor. A second N-channel MOS transistor is connected in parallel with the first N-channel MOS transistor as an auxiliary transistor. When the level of the input signal changes to switch one of the first P-channel MOS transistor and N-channel MOS transistor from an OFF state to an ON state, a drive switching control block delivers a signal to one of the auxiliary transistors connected in parallel with the switched one of the first P-channel MOS transistor and N-channel MOS transistor, for holding the one of the auxiliary transistors in an ON state over a predetermined time period.
    • 提供了一种输出缓冲器电路,其能够在输入信号的电平变化时获得大的驱动功率,同时允许通过电流以抑制的量流动。 第一P沟道MOS晶体管和第一N沟道MOS晶体管与电源串联连接。 一对晶体管通过输入信号专门接通和关断,使得第一和第二开关元件不同时导通或截止,以从第一和第二开关之间的公共端传送对应于输入信号的输出信号 元素。 第二P沟道MOS晶体管与作为辅助晶体管的第一P沟道MOS晶体管并联连接。 第二N沟道MOS晶体管与作为辅助晶体管的第一N沟道MOS晶体管并联连接。 当输入信号的电平变化以将第一P沟道MOS晶体管和N沟道MOS晶体管中的一个从OFF状态切换到ON状态时,驱动切换控制块将信号传递到连接在其中的辅助晶体管之一 与第一P沟道MOS晶体管和N沟道MOS晶体管中的一个开关并联,用于将一个辅助晶体管保持在预定时间段内的导通状态。
    • 36. 发明授权
    • Semiconductor device with element window defined by closed loop conductor
    • 具有由闭环导体限定的元件窗的半导体器件
    • US5804857A
    • 1998-09-08
    • US699995
    • 1996-08-20
    • Nobuaki Tsuji
    • Nobuaki Tsuji
    • H01L29/73H01L21/331H01L21/336H01L21/76H01L21/822H01L27/04H01L29/06H01L29/40H01L29/423H01L29/78H01L29/8605H01L29/76H01L29/94
    • H01L29/402H01L29/4238H01L29/8605
    • A semiconductor device, which acts as a resistor element, is constructed using a semiconductor substrate, a well region, a field insulation film having an element hole, a lamination layer and an impurity-doped region. The lamination layer is made by laminating a conductor layer on an insulation film, wherein the lamination layer has a closed-loop shape to cover overall periphery of an edge portion of the element hole. The impurity-doped region is formed on the well region in a self-aligned relationship with the lamination layer, wherein a P-N junction is formed between the impurity-doped region and well region with respect to the element hole and is terminated inside of the edge portion of the element hole. Another semiconductor device, which acts as a MOS transistor, is constructed using a conductor layer having a closed-loop shape, a source region and a drain region in addition to the semiconductor substrate, well region and field insulation film. Both of the source region and drain region are formed on the well region by effecting an impurity doping process and are formed in a self-aligned relationship with the closed-loop shape of the conductor layer and element hole. Further, a P-N Junction, which lies between the drain region and well region, is terminated inside of the edge portion of the element hole. Thus, it is possible to reduce dispersion in measurements of the P-N junctions and to improve reversal characteristics in the semiconductor devices.
    • 作为电阻元件的半导体器件使用半导体衬底,阱区,具有元件孔的场绝缘膜,层叠层和杂质掺杂区构成。 层叠层通过在绝缘膜上层叠导体层而制成,其中层叠层具有闭环形状以覆盖元件孔的边缘部分的整个周边。 杂质掺杂区域以与层叠层自对准的关系形成在阱区上,其中在杂质掺杂区域和阱区域之间相对于元件孔形成PN结,并且终止于边缘内部 元件孔的一部分。 作为MOS晶体管的另一个半导体器件除了半导体衬底,阱区和场绝缘膜之外,还使用具有闭环形状,源极区和漏极区的导体层构成。 通过进行杂质掺杂工艺,在阱区域上形成源极区域和漏极区域,并且与导体层和元件孔的闭环形状以自对准关系形成。 此外,位于漏极区域和阱区域之间的P-N结端接在元件孔的边缘部分的内部。 因此,可以减少P-N结的测量中的色散并改善半导体器件的反转特性。
    • 39. 发明授权
    • Silver halide photographic light-sensitive material
    • 卤化银照相感光材料
    • US5286619A
    • 1994-02-15
    • US44952
    • 1993-04-09
    • Nobuaki Tsuji
    • Nobuaki Tsuji
    • G03C1/76G03C1/89
    • G03C1/895G03C1/7614G03C1/89
    • A silver halide photographic light-sensitive material excellent in antistatic property and evelopment uniformity is provided, comprising a support having on one side thereof hydrophilic colloidal layers including a silver halide emulsion layer, which is exposed and processed with an automatic processing machine, wherein at least one of the hydrophilic layers contains a water-soluble polymer represented by formula [I] or a water-soluble polymer having a repeating unit represented by formula [II], and a nonionic surfactant represented by formula [IIIa], [IIIb] or [IIIc]. ##STR1##
    • 提供了抗静电性和显影均匀性优异的卤化银摄影感光材料,其包含一个支撑体,其一侧具有包括用自动处理机曝光和加工的卤化银乳剂层的亲水性胶体层,其中至少 亲水层之一含有由式(I)表示的水溶性聚合物或具有由式(II)表示的重复单元的水溶性聚合物和由式(IIIa),(IIIb)或(IIIb)表示的非离子表面活性剂 IIIc)。 (*化学结构*)(I)(*化学结构*)(II)(*化学结构*)(IIIa)(*化学结构*)(IIIb)(*化学结构*)(IIIc)